Design of a realistic test simulator for a built-in self test environment

A Ahmad, D Al-Abri - The Journal of Engineering Research …, 2010 - journals.squ.edu.om
This paper presents a realistic test approach suitable to Design For Testability (DFT) and
Built-In Self Test (BIST) environments. The approach is culminated in the form of a test …

Structural fault collapsing by superposition of BDDs for test generation in digital circuits

R Ubar, D Mironov, J Raik… - 2010 11th International …, 2010 - ieeexplore.ieee.org
The paper presents a new structural fault-independent fault collapsing method based on the
topology analysis of the circuit, which has linear complexity. The minimal necessary set of …

Turbo Tester–diagnostic package for research and training

M Aarna, E Ivask, A Jutman, E Orasson… - Радиоэлектроника и …, 2003 - cyberleninka.ru
This paper describes a diagnostic software package called Turbo Tester. It contains a variety
of tools related to the area of testing and diagnosis of integrated circuits. The range of tools …

Overview about low-level and high-level decision diagrams for diagnostic modeling of digital systems

R Ubar - Facta universitatis-series: Electronics and Energetics, 2011 - doiserbia.nb.rs
BDDs have become the state-of-the-art data structure in VLSI CAD. In this paper, a special
class of BDDs is presented called Structurally Synthesized BDDs (SSBDD). The idea of …

[PDF][PDF] Canonical representations of high-level decision diagrams.

A Karputkin, R Ubar, J Raik, M Tombak - Estonian Journal of Engineering, 2010 - kirj.ee
In this paper we give a short overview of the decision diagrams, and define a special class of
high-level decision diagrams (HLDD) for formal representation of digital systems. We show …

Fault Collapsing in Digital Circuits Using Fast Fault Dominance and Equivalence Analysis with SSBDDs

R Ubar, L Jürimägi, E Orasson, J Raik - … Security, and Low Power: 23rd IFIP …, 2016 - Springer
The paper presents a new method and an algorithm for structural fault collapsing to reduce
the search space for test generation, to speed up fault simulation and to make the fault …

[PDF][PDF] Optimization of structurally synthesized BDDs

R Ubar, T Vassiljeva, J Raik, A Jutman… - Proc. 4th IASTED …, 2004 - researchgate.net
ABSTRACT Binary Decision Diagrams present an efficient way of modeling digital systems
for simulation purposes. In order to take into account the need of representing faults directly …

[PDF][PDF] Design of an e-learning process in the area of digital system testing

A Ahmad, D Al-Abri, MM Al-Ramhi - Presented and Published in the …, 2006 - academia.edu
ABSTRACT A component of an ELearning environment process is presented for teaching
circuit simulation (truth table), test generation and fault diagnosis in digital circuits. A low …

Structurally synthesized multiple input BDDs for simulation of digital circuits

R Ubar, D Mironov, J Raik… - 2009 16th IEEE …, 2009 - ieeexplore.ieee.org
Binary decision diagrams (BDD) have become the state-of-the-art data structure in VLSI
CAD for representation and manipulation of Boolean Functions. For verification, fault …

Decision diagrams: From a mathematical notion to engineering applications

RS Stanković, R Ubar, JT Astola - Facta universitatis-series …, 2011 - doiserbia.nb.rs
The paper presents a historical perspective to the theory of decision diagrams from the first
definitions of the trees in mathematics related to the representations of discrete sets to the …