[BOOK][B] VLSI test principles and architectures: design for testability
This book is a comprehensive guide to new DFT methods that will show the readers how to
design a testable and quality product, drive down test cost, improve product quality and …
design a testable and quality product, drive down test cost, improve product quality and …
Testing embedded-core based system chips
Advances in semiconductor process and design technology enable the design of complex
system chips. Traditional IC design in which every circuit is designed from scratch and reuse …
system chips. Traditional IC design in which every circuit is designed from scratch and reuse …
Test wrapper and test access mechanism co-optimization for system-on-chip
Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip
(SOC) test architecture. Prior research has concentrated on only one aspect of the …
(SOC) test architecture. Prior research has concentrated on only one aspect of the …
[BOOK][B] System-on-chip test architectures: nanometer design for testability
LT Wang, CE Stroud, NA Touba - 2010 - books.google.com
Modern electronics testing has a legacy of more than 40 years. The introduction of new
technologies, especially nanometer technologies with 90nm or smaller geometry, has …
technologies, especially nanometer technologies with 90nm or smaller geometry, has …
A set of benchmarks for modular testing of SOCs
EJ Marinissen, V Iyengar… - Proceedings …, 2002 - ieeexplore.ieee.org
This paper presents the ITC'02 SOC test benchmarks. The purpose of this new benchmark
set is to stimulate research into new methods and tools for modular testing of SOCs and to …
set is to stimulate research into new methods and tools for modular testing of SOCs and to …
An efficient test vector compression scheme using selective Huffman coding
A Jas, J Ghosh-Dastidar, ME Ng… - IEEE transactions on …, 2003 - ieeexplore.ieee.org
This paper presents a compression/decompression scheme based on selective Huffman
coding for reducing the amount of test data that must be stored on a tester and transferred to …
coding for reducing the amount of test data that must be stored on a tester and transferred to …
A structured and scalable mechanism for test access to embedded reusable cores
EJ Marinissen, R Arendsen, G Bos… - … 1998 (IEEE Cat. No …, 1998 - ieeexplore.ieee.org
The main objective of core-based IC design is improvement of design efficiency and time-to-
market. In order to prevent test development from becoming the bottleneck in the entire …
market. In order to prevent test development from becoming the bottleneck in the entire …
Wrapper design for embedded core test
A wrapper is a thin shell around the core, that provides the switching between functional,
and core-internal and core-external test modes. Together with a test access mechanism …
and core-internal and core-external test modes. Together with a test access mechanism …
Frequency-directed run-length (FDR) codes with application to system-on-a-chip test data compression
A Chandra, K Chakrabarty - Proceedings 19th IEEE VLSI Test …, 2001 - ieeexplore.ieee.org
We showed recently that Golomb codes can be used for efficiently compressing system-on-a-
chip test data. We now present a new class of variable-to-variable-length compression …
chip test data. We now present a new class of variable-to-variable-length compression …
Test scheduling for core-based systems using mixed-integer linear programming
K Chakrabarty - IEEE Transactions on Computer-aided design …, 2000 - ieeexplore.ieee.org
We present optimal solutions to the test scheduling problem for core-based systems. Given a
set of tasks (test sets for the cores), a set of test resources (eg, test buses, BIST hardware) …
set of tasks (test sets for the cores), a set of test resources (eg, test buses, BIST hardware) …