A task-based greedy scheduling algorithm for minimizing energy of mapreduce jobs
MapReduce and its open source implementation, Hadoop, have gained widespread
adoption for parallel processing of big data jobs. Since the number of such big data jobs is …
adoption for parallel processing of big data jobs. Since the number of such big data jobs is …
Early-stage definition of LPX: A low power issue-execute processor
We present the high-level microarchitecture of LPX: a low-power issue-execute processor
prototype that is being designed by a joint industry-academia research team. LPX …
prototype that is being designed by a joint industry-academia research team. LPX …
Cache aging reduction with improved performance using dynamically re-sizable cache
Aging of transistors is a limiting factor for long term reliability of devices in sub-100nm
technologies. It's a worst-case metric where the lifetime of a device is determined by the …
technologies. It's a worst-case metric where the lifetime of a device is determined by the …
Leakage reduction techniques in a 0.13 um SRAM cell
S Romanovsky, A Achyuthan… - … Conference on VLSI …, 2004 - ieeexplore.ieee.org
SRAM standby leakage is very becoming critical with technology scaling to meet the
industry's demanding low power requirements. This paper discusses some of the leakage …
industry's demanding low power requirements. This paper discusses some of the leakage …
Architectural approaches to reduce leakage energy in caches
SH Tadas, C Chakrabarti - 2002 IEEE International Symposium …, 2002 - ieeexplore.ieee.org
In this paper, we present two methods to reduce leakage energy by dynamically resizing the
cache during program execution. The first method monitors the miss rate of the individual …
cache during program execution. The first method monitors the miss rate of the individual …
Deep submicron embedded SRAM design issues
S Natarajan, S Romanovsky… - … Conference on Solid …, 2004 - ieeexplore.ieee.org
Deep submicron embedded SRAM design issues Page 1 DEEP SUBMICRON EMBEDDED SRAM
DESIGN ISSUES Sreedhar Natara jan, Sergey Romanovsky, Arun Achyuth.:m MoSys …
DESIGN ISSUES Sreedhar Natara jan, Sergey Romanovsky, Arun Achyuth.:m MoSys …
Dynamic tag-check omission: A low power instruction cache architecture exploiting execution footprints
This paper proposes an architecture for low-power direct-mapped instruction caches, called
“history-based tag-comparison (HBTC) cache”. The HBTC cache attempts to detect and omit …
“history-based tag-comparison (HBTC) cache”. The HBTC cache attempts to detect and omit …
[PDF][PDF] Multi-criteria optimization for energy-efficient multi-core systems-on-chip
H Mahmood - 2014 - tesidottorato.depositolegale.it
The steady downscaling of transistor dimensions has made possible the evolutionary
progress leading to today's high-performance multi-GHz microprocessors and corebased …
progress leading to today's high-performance multi-GHz microprocessors and corebased …
[CITATION][C] Adaptive processing: Dynamically tuning processor resources for energy efficiency
DH Albonesi, R Balasubramonian, S Dropsho… - IEEE Comput, 2003