Design and implementation of a second order PLL based frequency synthesizer for implantable medical devices
In this paper, a low power 450 MHz frequency synthesizer for implantable medical device
(IMD) is presented. A current-reuse LC voltage-controlled oscillator is used to lower the …
(IMD) is presented. A current-reuse LC voltage-controlled oscillator is used to lower the …
A low-voltage design of controller-based ADPLL for implantable biomedical devices
A low-voltage controller-based all-digital phase-locked loop (ADPLL) utilized in the medical
implant communication service (MICS) frequency band is designed. The controller-based …
implant communication service (MICS) frequency band is designed. The controller-based …
Insights into the Ultra-Steep Subthreshold Slope Gate-all-around Feedback-FET for memory and sensing applications
Ultra-steep subthreshold slope FBFETs are promising candidates for next-generation
memory and sensing devices. The characteristic of Subthreshold slope less than 10mV/dec …
memory and sensing devices. The characteristic of Subthreshold slope less than 10mV/dec …
A TDC-less all-digital phase locked loop for medical implant applications
A TDC-less, ultra-low area and low power all-digital phase locked loop (ADPLL) has been
designed for use in biomedical implant transceivers. The proposed ADPLL eliminates the …
designed for use in biomedical implant transceivers. The proposed ADPLL eliminates the …
A107 µW MedRadio injection-locked clock multiplier with a CTAT-biased 126 ppm/° C ring oscillator
This paper presents a 400 MHz open-loop injectionlocked clock multiplier (ILCM) with low-
power and fast settling time. A one-time DCO calibration and novel temperature …
power and fast settling time. A one-time DCO calibration and novel temperature …
[PDF][PDF] A low phase noise CMOS ring VCO for short range device application
BS Choudhury, S Maity - Conf. proceedings, electrical electronics …, 2015 - researchgate.net
A low noise ring VCO architecture is proposed in this paper. The new VCO architecture uses
a differential CMOS logic. The proposed VCO works at 179MHz to 438MHz by varying the …
a differential CMOS logic. The proposed VCO works at 179MHz to 438MHz by varying the …
A low power frequency synthesizer for biosensor applications in the MedRadio band
AR Gundla, T Chen - 2015 IEEE 58th International Midwest …, 2015 - ieeexplore.ieee.org
With the growing applications of biosensors, there is growing desire for wireless interface to
integrated biosensors to the outside world. This paper proposes a multichannel PLL for …
integrated biosensors to the outside world. This paper proposes a multichannel PLL for …
A low-voltage PLL design using a new calibration technique for low-power implantable biomedical systems
YL Lo, WH Ho - Circuits, Systems, and Signal Processing, 2017 - Springer
This paper describes a low-voltage phase-locked loop (PLL) design using a new calibration
technique for low-power implantable biomedical systems. The proposed PLL uses a …
technique for low-power implantable biomedical systems. The proposed PLL uses a …
A design of 0.7-V 400-MHz all-digital phase-locked loop for implantable biomedical devices
A low-voltage controller-based all-digital phase-locked loop (ADPLL) utilized in the medical
implant communication service (MICS) frequency band was designed in this study. In the …
implant communication service (MICS) frequency band was designed in this study. In the …
A 224–448 MH z low‐power fully integrated phase‐locked loop using 0.18‐μm CMOS process
JH Tsai, CL Lin, YT Kuo - Microwave and Optical Technology …, 2017 - Wiley Online Library
Abstract A 224‐448 MHz low‐power fully integrated phase‐locked loop (PLL) is designed
and implemented in standard 0.18‐μm CMOS process. For wide tuning rage and compact …
and implemented in standard 0.18‐μm CMOS process. For wide tuning rage and compact …