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[КНИГА][B] Switching theory for logic synthesis
T Sasao - 2012 - books.google.com
Switching Theory for Logic Synthesis covers the basic topics of switching theory and logic
synthesis in fourteen chapters. Chapters 1 through 5 provide the mathematical foundation …
synthesis in fourteen chapters. Chapters 1 through 5 provide the mathematical foundation …
Multilevel logic synthesis
RK Brayton, GD Hachtel… - Proceedings of the …, 1990 - ieeexplore.ieee.org
A survey of logic synthesis techniques for multilevel combinational logic is presented. The
goal is to provide more in-depth background and perspective for people interested in …
goal is to provide more in-depth background and perspective for people interested in …
Task scheduling and voltage selection for energy minimization
In this paper, we present a two-phase framework that integrates task assignment, ordering
and voltage selection (VS) together to minimize energy consumption of real-time dependent …
and voltage selection (VS) together to minimize energy consumption of real-time dependent …
[КНИГА][B] Logic synthesis for asynchronous controllers and interfaces
J Cortadella, M Kishinevsky, A Kondratyev, L Lavagno… - 2012 - books.google.com
This book is the result of a long friendship, of a broad international co operation, and of a
bold dream. It is the summary of work carried out by the authors, and several other wonderful …
bold dream. It is the summary of work carried out by the authors, and several other wonderful …
Microarchitecture optimizations for exploiting memory-level parallelism
Y Chou, B Fahs, S Abraham - ACM SIGARCH Computer Architecture …, 2004 - dl.acm.org
The performance of memory-bound commercial applicationssuch as databases is limited by
increasing memory latencies. Inthis paper, we show that exploiting memory-level parallelism …
increasing memory latencies. Inthis paper, we show that exploiting memory-level parallelism …
Minimal assignments for bounded model checking
A traditional counterexample to a linear-time safety property shows the values of all signals
at all times prior to the error. However, some signals may not be critical to causing the …
at all times prior to the error. However, some signals may not be critical to causing the …
On solving covering problems
O Coudert - Proceedings of the 33rd Annual Design Automation …, 1996 - dl.acm.org
The set covering problem and the minimum cost assignment problem (respectively known
as unate and binate covering problem) arise throughout the logic synthesis ow. This paper …
as unate and binate covering problem) arise throughout the logic synthesis ow. This paper …
[КНИГА][B] Sequential logic synthesis
3. 2 Input Encoding Targeting Two-Level Logic........ 27 3. 2. 1 One-Hot Coding and Multiple-
Valued Minimization 28 3. 2. 2 Input Constraints and Face Embedding 30 3. 3 Satisfying …
Valued Minimization 28 3. 2. 2 Input Constraints and Face Embedding 30 3. 3 Satisfying …
Approximate logic synthesis under general error magnitude and frequency constraints
Recent interest in approximate circuit design is driven by its potential for large energy
savings. In this paper, we address the problem of approximate logic synthesis (ALS). ALS is …
savings. In this paper, we address the problem of approximate logic synthesis (ALS). ALS is …
[PDF][PDF] Logic synthesis for engineering change
C Lin, KC Chen, SC Chang… - Proceedings of the …, 1995 - dl.acm.org
In the process of VLSI design, specifications are often changed. It is desirable that such
changes will not lead to a very di erent design so that a large part of engineering e ort can …
changes will not lead to a very di erent design so that a large part of engineering e ort can …