Wireless sensor networks (WSNs) are typically used with dynamic conditions of task-related
environments for sensing (monitoring) and gathering of raw sensor data for subsequent …

Networks-on-Chip constitute the interconnection architecture of future, massively parallel
multiprocessors that assemble hundreds to thousands of processing cores on a single chip …

Process scaling has given designers billions of transistors to work with. As feature sizes near
the atomic scale, extensive variation and wearout inevitably make margining uneconomical …

In this paper, we propose a distributed routing algorithm for vertically partially connected
regular 2D topologies of different shapes and sizes (eg, 2D mesh, torus, ring). The …

Recently, IBM, Google, and Intel showcased quantum computers ranging from 49 to 72
qubits. While these systems represent a significant milestone in the advancement of …

The widespread proliferation of the Chip Multi-Processor (CMP) paradigm has cemented the
criticality of the on-chip interconnection fabric. The Network-on-Chip (NoC) is becoming …

Continuing decrease in the feature size of integrated circuits leads to increases in
susceptibility to transient and permanent faults. This paper proposes a fault-tolerant solution …

Aggressive transistor scaling continues to drive increasingly complex digital designs. The
large number of transistors available today enables the development of chip multiprocessors …

Increasing communication overheads are already threatening computer system scaling. One
approach to dramatically reduce communication overheads is waferscale processing …

In this paper, we propose a covert threat model for MPSoCs designed using 3rd party
Network-on-Chips (NoC). We illustrate that a malicious NoC can disrupt the availability of on …