Map** interleaving laws to parallel turbo and LDPC decoder architectures

A Tarable, S Benedetto… - IEEE Transactions on …, 2004 - ieeexplore.ieee.org
For high-data-rate applications, the implementation of iterative turbo-like decoders requires
the use of parallel architectures posing some collision-free constraints to the reading/writing …

Iterative decoding of concatenated convolutional codes: Implementation issues

E Boutillon, C Douillard, G Montorsi - Proceedings of the IEEE, 2007 - ieeexplore.ieee.org
This tutorial paper gives an overview of the implementation aspects related to turbo
decoders, where the term turbo generally refers to iterative decoders intended for parallel …

[SÁCH][B] Turbo code applications

K Sripimanwat - 2005 - Springer
Turbo Code Applications: a journey from a paper to realization presents contemporary
applications of turbo codes in thirteen technical chapters. Each chapter focuses on a …

Network-on-chip-centric approach to interleaving in high throughput channel decoders

C Neeb, MJ Thul, N Wehn - 2005 IEEE International …, 2005 - ieeexplore.ieee.org
Reliable wireless communication needs efficient channel coding schemes like turbo and
LDPC codes. During decoding, data is exchanged iteratively between component decoders …

Butterfly and Benes-based on-chip communication networks for multiprocessor turbo decoding

H Moussa, O Muller, A Baghdadi… - … Design, Automation & …, 2007 - ieeexplore.ieee.org
Several research activities have recently emerged aiming to propose multiprocessor
implementations in order to achieve flexible and high throughput parallel iterative decoding …

From parallelism levels to a multi-ASIP architecture for turbo decoding

O Muller, A Baghdadi… - IEEE transactions on very …, 2008 - ieeexplore.ieee.org
Emerging digital communication applications and the underlying architectures encounter
drastically increasing performance and flexibility requirements. In this paper, we present a …

ASIP-based multiprocessor SoC design for simple and double binary turbo decoding

O Muller, A Baghdadi… - Proceedings of the Design …, 2006 - ieeexplore.ieee.org
This paper presents a new multiprocessor platform for high throughput turbo decoding. The
proposed platform is based on a new configurable ASIP combined with an efficient memory …

Exploring parallel processing levels for convolutional turbo decoding

O Muller, A Baghdadi… - 2006 2nd International …, 2006 - ieeexplore.ieee.org
In forward error correction, convolutional turbo codes were introduced to increase error
correction capability approaching the Shannon bound. Decoding of these codes, however …

Contention-free interleavers for high-throughput turbo decoding

A Nimbalker, TK Blankenship, B Classon… - IEEE Transactions …, 2008 - ieeexplore.ieee.org
This paper presents a low-complexity interleaver design that facilitates the high throughput
turbo decoding required for next generation wireless systems. Specifically, it addresses the …

Maximum spread of D-dimensional multiple turbo codes

E Boutillon, D Gnaedig - IEEE transactions on communications, 2005 - ieeexplore.ieee.org
This letter presents the mathematical framework involved in the determination of an upper
bound of the maximum spread value of a D-dimensional turbo code of frame size N. This …