DAMOV: A new methodology and benchmark suite for evaluating data movement bottlenecks

GF Oliveira, J Gómez-Luna, L Orosa, S Ghose… - IEEE …, 2021 - ieeexplore.ieee.org
Data movement between the CPU and main memory is a first-order obstacle against improv
ing performance, scalability, and energy efficiency in modern systems. Computer systems …

MIMDRAM: An end-to-end processing-using-DRAM system for high-throughput, energy-efficient and programmer-transparent multiple-instruction multiple-data …

GF Oliveira, A Olgun, AG Yağlıkçı… - … Symposium on High …, 2024 - ieeexplore.ieee.org
Processing-using-DRAM (PUD) is a processing-in-memory (PIM) approach that uses a
DRAM array's massive internal parallelism to execute very-wide (eg, 16,384-262,144-bit …

Memory-Centric Computing: Recent Advances in Processing-in-DRAM

O Mutlu, A Olgun, GF Oliveira… - 2024 IEEE International …, 2024 - ieeexplore.ieee.org
Memory-centric computing aims to enable computation capability in and near all places
where data is generated and stored. As such, it can greatly reduce the large negative …

Livia: Data-centric computing throughout the memory hierarchy

E Lockerman, A Feldmann, M Bakhshalipour… - Proceedings of the …, 2020 - dl.acm.org
In order to scale, future systems will need to dramatically reduce data movement. Data
movement is expensive in current designs because (i) traditional memory hierarchies force …

Towards efficient sparse matrix vector multiplication on real processing-in-memory architectures

C Giannoula, I Fernandez, J Gómez-Luna… - ACM SIGMETRICS …, 2022 - dl.acm.org
Several manufacturers have already started to commercialize near-bank Processing-In-
Memory (PIM) architectures, after decades of research efforts. Near-bank PIM architectures …

Infinity stream: Portable and programmer-friendly in-/near-memory fusion

Z Wang, C Liu, A Arora, L John… - Proceedings of the 28th …, 2023 - dl.acm.org
In-memory computing with large last-level caches is promising to dramatically alleviate data
movement bottlenecks and expose massive bitline-level parallelization opportunities …

NDPBridge: Enabling Cross-Bank Coordination in Near-DRAM-Bank Processing Architectures

B Tian, Y Li, L Jiang, S Cai… - 2024 ACM/IEEE 51st …, 2024 - ieeexplore.ieee.org
Various near-data processing (NDP) designs have been proposed to alleviate the memory
wall challenge for data-intensive applications. Among them, near-DRAM-bank NDP …

Near-stream computing: General and transparent near-cache acceleration

Z Wang, J Weng, S Liu… - 2022 IEEE International …, 2022 - ieeexplore.ieee.org
Data movement and communication have become the primary bottlenecks in large multicore
systems. The near-data computing paradigm provides a solution: move computation to …

[LLIBRE][B] In-/near-memory Computing

D Fujiki, X Wang, A Subramaniyan, R Das - 2021 - Springer
This book provides a structured introduction of the key concepts and techniques that enable
in-/near-memory computing. For decades, processing-in-memory or near-memory …

Stream floating: Enabling proactive and decentralized cache optimizations

Z Wang, J Weng, J Lowe-Power, J Gaur… - … Symposium on High …, 2021 - ieeexplore.ieee.org
As multicore systems continue to grow in scale and on-chip memory capacity, the on-chip
network bandwidth and latency become problematic bottlenecks. Because of this …