Tradeoffs and optimization in analog CMOS design
DM Binkley - 2007 14th International Conference on Mixed …, 2007 - ieeexplore.ieee.org
The selection of drain current, inversion coefficient, and channel length for each MOS device
in an analog circuit results in significant tradeoffs in performance. The selection of inversion …
in an analog circuit results in significant tradeoffs in performance. The selection of inversion …
VHDL-AMS and Verilog-AMS as alternative hardware description languages for efficient modeling of multidiscipline systems
F Pêcheux, C Lallement… - IEEE transactions on …, 2005 - ieeexplore.ieee.org
This paper focuses on commonalities and differences between the two mixed-signal
hardware description languages, VHDL-AMS and Verilog-AMS, in the case of modeling …
hardware description languages, VHDL-AMS and Verilog-AMS, in the case of modeling …
A Sub- Voltage Reference Operating at 150 mV
We propose a subthreshold CMOS voltage reference operating with a minimum supply
voltage of only 150 mV, which is three times lower than the minimum value presently …
voltage of only 150 mV, which is three times lower than the minimum value presently …
An ultralow-power UHF transceiver integrated in a standard digital CMOS process: architecture and receiver
A broad range of high-volume consumer applications require low-power battery-operated
wireless microsystems and sensors. These systems should conciliate a sufficient battery …
wireless microsystems and sensors. These systems should conciliate a sufficient battery …
Optimizing drain current, inversion level, and channel length in analog CMOS design
DM Binkley, BJ Blalock, JM Rochelle - Analog Integrated Circuits and …, 2006 - Springer
This paper describes a methodology for selecting drain current, inversion level (represented
by inversion coefficient), and channel length for optimum performance tradeoffs in analog …
by inversion coefficient), and channel length for optimum performance tradeoffs in analog …
Low-noise analog channel for the readout of the Si (Li) detector of the GAPS experiment
This work is focused on the design and the experimental characterization of an analog
channel developed for the readout of lithium-drifted silicon detectors of the General …
channel developed for the readout of lithium-drifted silicon detectors of the General …
A compact non-quasi-static extension of a charge-based MOS model
This paper presents a new and simple compact model for the intrinsic metal oxide
semiconductor (MOS) transistor, which accurately takes into account the non quasistatic …
semiconductor (MOS) transistor, which accurately takes into account the non quasistatic …
Comparison of a BSIM3V3 and EKV MOSFET model for a 0.5/spl mu/m CMOS process and implications for analog circuit design
SC Terry, JM Rochelle, DM Binkley… - IEEE transactions on …, 2003 - ieeexplore.ieee.org
Design requirements for high-density detector front-ends and other high-performance
analog systems routinely force designers to operate devices in moderate inversion …
analog systems routinely force designers to operate devices in moderate inversion …
Design-oriented characterization of CMOS over the continuum of inversion level and channel length
DM Binkley, M Bucher, D Foty - ICECS 2000. 7th IEEE …, 2000 - ieeexplore.ieee.org
A methodology for small signal characterization of CMOS processes over the full range of
inversion level and channel length is presented. Measured transconductance and output …
inversion level and channel length is presented. Measured transconductance and output …
A picopower temperature‐compensated, subthreshold CMOS voltage reference
ABSTRACT A voltage reference consisting of only two nMOS transistors with different
threshold voltages is presented. Measurements performed on 23 samples from a single …
threshold voltages is presented. Measurements performed on 23 samples from a single …