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Performance optimization of VLSI interconnect layout
This paper presents a comprehensive survey of existing techniques for interconnect
optimization during the VLSI physical design process, with emphasis on recent studies on …
optimization during the VLSI physical design process, with emphasis on recent studies on …
Clock distribution networks in synchronous digital integrated circuits
Clock distribution networks synchronize the flow of data signals among synchronous data
paths. The design of these networks can dramatically affect system-wide performance and …
paths. The design of these networks can dramatically affect system-wide performance and …
Clock distribution design in VLSI circuits-an overview
Clock distribution networks synchronize the flow of data signals between data paths, and the
design of these networks can dramatically affect system wide performance and reliability …
design of these networks can dramatically affect system wide performance and reliability …
Zero-skew clock routing trees with minimum wirelength
The deferred-merge embedding (DME) algorithm is presented. In linear time, it embeds any
given connection topology into the Manhattan plane to create a clock tree with zero skew …
given connection topology into the Manhattan plane to create a clock tree with zero skew …
A clustering-based optimization algorithm in zero-skew routings
A zero-skew routing algorithm with clustering and improvement methods is proposed. This
algorithm generates a zero-skew routing in O (n log n) time for n pins, and it is proven that …
algorithm generates a zero-skew routing in O (n log n) time for n pins, and it is proven that …
Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects
Nonuniform thermal profiles on the substrate in high-performance ICs can significantly
impact the performance of global on-chip interconnects. This paper presents a detailed …
impact the performance of global on-chip interconnects. This paper presents a detailed …
ICCAD-2015 CAD contest in incremental timing-driven placement and benchmark suite
At modern technology nodes, improving routability and reducing total wirelength are no
longer sufficient to close timing. Incremental timing-driven placement (TDP) seeks to resolve …
longer sufficient to close timing. Incremental timing-driven placement (TDP) seeks to resolve …
Bounded-skew clock and Steiner routing
We study the minimum-cost bounded-skew routing tree problem under the pathlength
(linear) and Elmore delay models. This problem captures several engineering tradeoffs in …
(linear) and Elmore delay models. This problem captures several engineering tradeoffs in …
Clock-tree power optimization based on RTL clock-gating
As power consumption of the clock tree in modern VLSI designs tends to dominate,
measures must be taken to keep it under control. This paper introduces an approach for …
measures must be taken to keep it under control. This paper introduces an approach for …
Bilinear heterogeneous information machine for RGB-D action recognition
This paper proposes a novel approach to action recognition from RGB-D cameras, in which
depth features and RGB visual features are jointly used. Rich heterogeneous RGB and …
depth features and RGB visual features are jointly used. Rich heterogeneous RGB and …