One of the most popular methods for reliability assessment of digital circuits is Fault Injection
(FI) in which the behavior of the circuit is simulated in presence of faults. In this paper, we …

FPGA-based designs are more susceptible to single-event upsets (SEUs) compared to ASIC
designs. Soft error rate (SER) estimation is a crucial step in the design of soft error tolerant …

Soft errors due to cosmic particles are a growing reliability threat for VLSI systems. The
vulnerability of FPGA-based designs to soft errors is higher than ASIC implementations …

vi multiple system layers in an integrated fashion for reliability optimization under user-
provided tolerable performance overhead constraints. To enable this, this work addresses …

Fast, accurate, and detailed Soft Error Rate (SER) estimation of digital circuits is essential for
cost-efficient reliable design. A major step to accurately estimate a circuit SER is the …

Modern integrated circuits require careful attention to the soft errors resulting into bit upsets,
which are normally caused by alpha particle or neutron hits. These events, also referred to …

Radiation-induced soft errors are the major reliability threat for digital VLSI systems. In
particular, field-programmable gate-array (FPGA)-based designs are more susceptible to …

Soft error tolerant design becomes more crucial due to exponential increase in the
vulnerability of computer systems to soft errors. Accurate estimation of soft error rate (SER) …

Due to shrinking feature size and higher transistor count in a single chip in modern
fabrication technologies, power consumption and soft error reliability have become two …

Soft errors due to cosmic radiations are the main reliability threat during lifetime operation of
digital systems. Fast and accurate estimation of soft error rate (SER) is essential in obtaining …