DFT based atomic modeling and Analog/RF analysis of ferroelectric HfO2 based improved FET device

Y Pathak, BD Malhotra, R Chaujar - Physica Scripta, 2023 - iopscience.iop.org
In this study, we systematically investigated the Analog/RF and linearity parameter of SM
DGNCFET (single metal double gate negative capacitance field effect transistor) and DM …

Sensitivity analysis of TMD TFET based photo-sensor for visible light detection: A simulation study

S Tiwari, R Saha - Microelectronics Journal, 2024 - Elsevier
This paper reports the sensitivity analysis of double gate TFET using the Transition Metal Di
chalcogenide (TMD) material in photo sensitive region with the help of technology computer …

Exploration of temperature stability of linearity and RF performance metrics for PGP negative capacitance FET

S Chaudhary, B Dewan, D Singh… - Semiconductor …, 2023 - iopscience.iop.org
The present work focuses on investigating the performance of partial ground plane selective
buried oxide negative capacitance (NC) field-effect transistor (NCFET) electrical properties …

Impact of interface trap charges on analog/RF and linearity performances of PGP negative capacitance FET

S Chaudhary, B Dewan, D Singh, C Sahu… - Microelectronics …, 2023 - Elsevier
Here, we examine the impact of various trap charges on the baseline and NC PGPFET
(negative capacitance partial ground plane FET) by applying localized charges …

Impact of temperature sensitivity on dead channel junctionless FET for linearity and high frequency applications

S Chaudhary, B Dewan, D Singh… - … Science and Technology, 2024 - iopscience.iop.org
The operational framework of upcoming electronic devices is under examination to identify
substitutes for MOSFETs, aiming to decrease power densities and alleviate constraints on …

[HTML][HTML] Implementation and Comprehensive Investigation of Gate Engineered Si0. 1Ge0. 9/GaAs Charged Plasma Based JLTFET for Improved Analog/RF …

P Soni, A Jain, K Kumar, LK Soni, A Kumar… - Results in …, 2025 - Elsevier
This study introduces the Variable Length Dual Dielectric Material-Gate Spacer Engineering
Heterostructure Junction-Less Tunnel Field-Effect Transistor (VLDD-GSE-HJLTFET), a novel …

Performance investigation of different low power SRAM cell topologies using stacked-channel tri-gate junctionless FinFET

D Singh, S Chaudhary, B Dewan, M Yadav - Microelectronics Journal, 2024 - Elsevier
At the sub-22 nm technology node, junctionless FinFETs are regarded as advantageous
alternatives for conventional FinFET due to their simpler fabrication and uniform do** …

Core-shell architecture and channel suppression: unleashing the potential of SC_RCS_DGJLFET

A Himral, R Sharma, M Agarwal - Physica Scripta, 2024 - iopscience.iop.org
In this investigation, a suppressed channel-rectangular core–shell double gate junctionless
field effect transistor (SC_RCS_DGJLFET) is simulated to enhance the junctionless device's …

Comparative Evaluation of Ferroelectric Negative Capacitance MFMIS and MFIS Transistors for Analog/Radio-Frequency Applications

TT Cheng, Q Li, YX Yang… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
As the negative capacitance field-effect transistors (NCFETs) have extensive application
prospects and advanced technological support in the analog/radio-frequency (RF) domains …

Proposal and performance evaluation of delta doped negative capacitance tunneling field transistor: a simulation study

S Chaudhary, B Dewan, D Singh, C Sahu… - Micro and …, 2023 - Elsevier
Here we proposes and optimizes a delta doped dual spacer negative capacitance TFET to
improve ON current, steeper sub threshold slope, and ON to OFF current ratio. The inclusion …