In this paper, we propose Zero-Suppressed BDDs (O-Sup-BDDs), which are BDDs based on
a new reduction rule. This data structure brings unique and compact representation of sets …

Preprocessing has become a key component of the Boolean satisfiability (SAT) solving
workflow. In practice, preprocessing is situated between the encoding phase and the solving …

In many real-life problems, we are often faced with manipulating sets of combinations. In this
article, we study a special type of ordered binary decision diagram (OBDD), called zero …

SAT solvers are often challenged with very hard problems that remain unsolved after hours
of CPU time. The research community meets the challenge in two ways:(1) by improving the …

Spot is a library of model-checking algorithms started in 2003. This paper focuses on its
module for translating linear-time temporal logic (LTL) formulas into Büchi automata: one of …

Today, computational fluid dynamics (CFD) research is almost impossible without computer-
generated visualizations of the very large amounts of data resulting from numerical …

Abstract Zero-suppressed binary Decision Diagrams (ZDDs) have emerged as an efficient
way of solving problems in set theory. This tutorial presents ZDDs and assumes that the …

Reducing delay of a digital circuit is an important topic in logic synthesis for standard cells
and LUT-based FPGAs. This paper presents a simple, fast, and very efficient synthesis …

A program called MVSIS (Multi-Valued Sequential Interactive Synthesis) has been
developed which optimizes multi-level multi-valued (MV) networks. We describe what such a …

Bounded variable elimination is one of the most important preprocessing techniques in SAT
solving. It benefits from discovering functional dependencies in the form of definitions …