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ZnO nanowire optoelectronic synapse for neuromorphic computing
Advanced CMOS gate stack: Present research progress
The decreasing sizes in complementary metal oxide semiconductor (CMOS) transistor
technology require the replacement of SiO2 with gate dielectrics that have a high dielectric …
technology require the replacement of SiO2 with gate dielectrics that have a high dielectric …
[HTML][HTML] Metal-insulator-metal single electron transistors with tunnel barriers prepared by atomic layer deposition
Single electron transistors are nanoscale electron devices that require thin, high-quality
tunnel barriers to operate and have potential applications in sensing, metrology and beyond …
tunnel barriers to operate and have potential applications in sensing, metrology and beyond …
The effect of thermal treatment induced inter-diffusion at the interfaces on the charge trap** performance of HfO2/Al2O3 nanolaminate-based memory devices
The charge trap** memory devices based on different HfO 2/Al 2 O 3 nanolaminated
charge trap** layers were prepared and investigated. The memory device with 6 …
charge trap** layers were prepared and investigated. The memory device with 6 …
Outstanding memory characteristics with atomic layer deposited Ta2O5/Al2O3/TiO2/Al2O3/Ta2O5 nanocomposite structures as the charge trap** layer
A charge trap** memory device using Ta 2 O 5/Al 2 O 3/TiO 2/Al 2 O 3/Ta 2 O 5 (TATiAT)
nanocomposite high-k dielectrics as charge trap** layer (CTL) and amorphous Al 2 O 3 as …
nanocomposite high-k dielectrics as charge trap** layer (CTL) and amorphous Al 2 O 3 as …
Atomic layer-deposited Ta 2 O 5− x nano-islands for charge trap** memory devices
S Sun, L Gao, P Han, L Zhu, WM Li… - Journal of Materials …, 2024 - pubs.rsc.org
Charge trap** memory (CTM) boasts numerous advantages over conventional flash
memory, making it a suitable alternative. In this work, atomic layer-deposited Ta2O5− x nano …
memory, making it a suitable alternative. In this work, atomic layer-deposited Ta2O5− x nano …
Analysis of HfO2 charge trap** layer characteristics after UV treatment
The improvement in the charge storage characteristics in a non-volatile memory (NVM)
device employing an ultraviolet (UV)-treated hafnium oxide (HfO 2) layer as the charge …
device employing an ultraviolet (UV)-treated hafnium oxide (HfO 2) layer as the charge …
Ta2O5-TiO2 Composite Charge-trap** Dielectric for the Application of the Nonvolatile Memory
CY Wei, B Shen, P Ding, P Han, AD Li, YD ** memory devices with a structure Pt/Al2O3/(Ta2O5) x (TiO2) 1−
x/Al2O3/p-Si (x= 0.9, 0.75, 0.5, 0.25) were fabricated by using rf-sputtering and atomic layer …
x/Al2O3/p-Si (x= 0.9, 0.75, 0.5, 0.25) were fabricated by using rf-sputtering and atomic layer …
Carrier transport mechanisms of multilevel nonvolatile memory devices with a floating gate consisting of hybrid organic/inorganic nanocomposites
Nonvolatile memory devices based on a poly (4-vinylphenol)(PVP) layer containing Cu 2
ZnSnS 4 (CZTS) nanoparticles were fabricated by using a simple spin-coating method. An …
ZnSnS 4 (CZTS) nanoparticles were fabricated by using a simple spin-coating method. An …
The dominant factors affecting the memory characteristics of (Ta2O5) x (Al2O3) 1− x high-k charge-trap** devices
C Gong, Q Yin, X Ou, X Lan, J Liu, C Sun… - Applied Physics …, 2014 - pubs.aip.org
The prototypical charge-trap** memory devices with the structure p-Si/Al 2 O 3/(Ta 2 O 5)
x (Al 2 O 3) 1− x/Al 2 O 3/Pt (x= 0.5, 0.3, and 0.1) were fabricated by using atomic layer …
x (Al 2 O 3) 1− x/Al 2 O 3/Pt (x= 0.5, 0.3, and 0.1) were fabricated by using atomic layer …