The “memory wall” problem or so-called von Neumann bottleneck limits the efficiency of
conventional computer architectures, which move data from memory to CPU for …

Aggressive technology scaling over the years has helped improve processor performance
but has caused a reduction in processor reliability. Shrinking transistor sizes and lower …

In this paper, we explore the use of multi-band radio frequency interconnect (or RF-I) with
signal propagation at the speed of light to provide shortcuts in a many core network-on-chip …

As technology scales, GPUs are forecasted to incorporate an ever-increasing amount of
computing resources to support thread-level parallelism. But even with the best effort …

With the number of cores of chip multiprocessors (CMPs) rapidly growing as technology
scales down, connecting the different components of a CMP in a scalable and efficient way …

With the trend towards increasing number of processor cores in future chip architectures,
scalable directory-based protocols for maintaining cache coherence will be needed …

This work revisits the design of crossbar and high-radix interconnects in light of advances in
circuit and layout techniques that improve crossbar scalability, obviating the need for deep …

A key determinant of overall system performance and power dissipation is the cache
hierarchy since access to off-chip memory consumes many more cycles and energy than on …

Current network-on-chip designs in chip-multiprocessors are agnostic to application
requirements and hence are provisioned for the general case, leading to wasted energy and …

Networks-on-Chip (NoCs) are currently the paradigm of choice to interconnect the cores of a
chip multiprocessor. However, conventional NoCs may not suffice to fulfill the on-chip …