The ArchC architecture description language and tools
This paper presents an architecture description language (ADL) called ArchC, which is an
open-source SystemC-based language that is specialized for processor architecture …
open-source SystemC-based language that is specialized for processor architecture …
[ΒΙΒΛΙΟ][B] Processor description languages
Efficient design of embedded processors plays a critical role in embedded systems design.
Processor description languages and their associated specification, exploration and rapid …
Processor description languages and their associated specification, exploration and rapid …
ArchC: A SystemC-based architecture description language
This paper presents an architecture description language (ADL) called ArchC, which is an
open-source SystemC-based language that is specialized for processor architecture …
open-source SystemC-based language that is specialized for processor architecture …
Application of active contour models in medical image segmentation
Recent developments on medical imaging techniques have brought a completely new
research field on image processing. The principal aim is to improve medical diagnosis …
research field on image processing. The principal aim is to improve medical diagnosis …
Architecture description languages for programmable embedded systems
Embedded systems present a tremendous opportunity to customise designs by exploiting
the application behaviour. Shrinking time-to-market, coupled with short product lifetimes …
the application behaviour. Shrinking time-to-market, coupled with short product lifetimes …
Cycle-accurate performance modelling in an ultra-fast just-in-time dynamic binary translation instruction set simulator
Instruction set simulators (ISS) are vital tools for compiler and processor architecture design
space exploration and verification. State-of-the-art simulators using just-in-time (JIT) …
space exploration and verification. State-of-the-art simulators using just-in-time (JIT) …
Generalized just-in-time trace compilation using a parallel task farm in a dynamic binary translator
Dynamic Binary Translation (DBT) is the key technology behind cross-platform virtualization
and allows software compiled for one Instruction Set Architecture (ISA) to be executed on a …
and allows software compiled for one Instruction Set Architecture (ISA) to be executed on a …
Fine-grained application source code profiling for ASIP design
K Karuri, MA Al Faruque, S Kraemer… - Proceedings of the …, 2005 - dl.acm.org
Current Application Specific Instruction set Processor (ASIP) design methodologies are
mostly based on iterative architecture exploration that uses Architecture Description …
mostly based on iterative architecture exploration that uses Architecture Description …
Fast cycle-approximate instruction set simulation
B Franke - Proceedings of the 11th international workshop on …, 2008 - dl.acm.org
Instruction set simulators are indispensable tools in both ASIP design space exploration and
the software development and optimisation process for existing platforms. Despite the recent …
the software development and optimisation process for existing platforms. Despite the recent …
High speed CPU simulation using LTU dynamic binary translation
D Jones, N Topham - … on High-Performance Embedded Architectures and …, 2009 - Springer
In order to increase the speed of dynamic binary translation based simulators we consider
the translation of large translation units consisting of multiple blocks. In contrast to other …
the translation of large translation units consisting of multiple blocks. In contrast to other …