Low latency and division free Gauss–Jordan solver in floating point arithmetic
JP David - Journal of Parallel and Distributed Computing, 2017 - Elsevier
In many applications, the solution of a linear system is computed with Gaussian elimination
followed by back-substitution, or Gauss–Jordan elimination. The latter is intrinsically more …
followed by back-substitution, or Gauss–Jordan elimination. The latter is intrinsically more …
Reducing memory requirements for high-performance and numerically stable gaussian elimination
D Boland - Proceedings of the 2016 ACM/SIGDA International …, 2016 - dl.acm.org
Gaussian elimination is a well-known technique to compute the solution to a system of linear
equations and boosting its performance is highly desirable. While straightforward parallel …
equations and boosting its performance is highly desirable. While straightforward parallel …
Low latency solver for linear equation systems in floating point arithmetic
JP David - 2015 International Conference on ReConFigurable …, 2015 - ieeexplore.ieee.org
Some applications, especially real time simulation systems, require to compute a linear
system's solution in a very short amount of time. FPGA are well known to offer low latency …
system's solution in a very short amount of time. FPGA are well known to offer low latency …
Fpga hil simulation of a linear system block for strongly coupled system applications
This paper introduces a hardware simulation flow that is based on the **linx System
Generator Tool (XSG), of an architecture for solving dense linear systems, presented as a …
Generator Tool (XSG), of an architecture for solving dense linear systems, presented as a …
Hardware implementation of GMDH-type artificial neural networks and its use to predict approximate three-dimensional structures of proteins
Implementation of artificial neural networks in software on general purpose computer
platforms are brought to an advanced level both in terms of performance and accuracy …
platforms are brought to an advanced level both in terms of performance and accuracy …
Hardware architecture of the EKF prediction stage applied to mobile robot localization
L Contreras, S Cruz, JMST Motta… - 2015 IEEE 6th Latin …, 2015 - ieeexplore.ieee.org
This work presents an FPGA-based Hardware Architecture to implement the Prediction
Stage of the Extended Kalman Filter (EKF) applied to the localization problem in mobile …
Stage of the Extended Kalman Filter (EKF) applied to the localization problem in mobile …
On hardware solution of dense linear systems via Gauss-Jordan elimination
Gauss-Jordan Elimination (GJE) is a popular method for solving systems of linear equations.
Much work has been done to design high throughput, low cost, FPGA-based architectures …
Much work has been done to design high throughput, low cost, FPGA-based architectures …
On kernel acceleration of electromagnetic solvers via hardware emulation
Finding new techniques to accelerate electromagnetic (EM) simulations has become a
necessity nowadays due to its frequent usage in industry. As they are mainly based on …
necessity nowadays due to its frequent usage in industry. As they are mainly based on …
Systolic parallel architecture for brute-force autoregressive signal modeling
NAS Alwan - Computers & Electrical Engineering, 2013 - Elsevier
The paper describes a parallel architecture in the form of a systolic automaton consisting of
three distinct stages for the computation of the model parameters of an autoregressive (AR) …
three distinct stages for the computation of the model parameters of an autoregressive (AR) …
Redes neurais baseadas no método de grupo de manipulação de dados: treinamento, implementações e aplicações
ALS Braga - 2013 - icts.unb.br
O Método de Grupo para Manipulação de Dados (GMDH-Group Method of Data Handling) é
um modelo de rede neural artificial (RNA) constituído de neurônios compostos por …
um modelo de rede neural artificial (RNA) constituído de neurônios compostos por …