Systematic and optimal design of CMOS two-stage opamps with hybrid cascode compensation
This paper presents a systematic and optimal design of hybrid cascode compensation
method which is used in fully differential two-stage CMOS operational transconductance …
method which is used in fully differential two-stage CMOS operational transconductance …
A 20-MS/s to 40-MS/s reconfigurable pipeline ADC implemented with parallel OTA scaling
A reconfigurable 12-b pipeline analog-to-digital converter (ADC) implemented by enabling
or disabling MDAC OTAs in parallel is presented. Power scaling is achieved without varying …
or disabling MDAC OTAs in parallel is presented. Power scaling is achieved without varying …
Power and area efficient pipelined ADC stage in digital CMOS technology
ABSTRACT A power and area efficient metal-oxide semiconductor field-effect transistor
(MOSFET)-only 1.5-bit fully differential pipelined analog-to-digital converter (ADC) stage is …
(MOSFET)-only 1.5-bit fully differential pipelined analog-to-digital converter (ADC) stage is …
Systematic design for power minimization of pipelined analog-to-digital converters
In this paper a general method to design a pipelined ADC with minimum power consumption
is presented. By expressing the total power consumption and the total input-referred noise of …
is presented. By expressing the total power consumption and the total input-referred noise of …
A low power 1-V 10-bit 40-MS/s pipeline ADC
A low power 10 bit, 40 MS/s pipeline analog to digital converter is presented. A number of
low-power techniques are proposed in various levels of abstraction. In circuit level, a low …
low-power techniques are proposed in various levels of abstraction. In circuit level, a low …
Design of power, dynamic range, bandwidth and noise scalable ADCs
The proliferation of portable electronic devices with high data-rate wireless communication
capabilities and the increasing emphasis on energy efficiency is continuously applying …
capabilities and the increasing emphasis on energy efficiency is continuously applying …
Indirect Miller effect based compensation in Low power two-stage operational Amplifiers
M Mohammadpour… - … Conference on Multimedia …, 2012 - ieeexplore.ieee.org
In this paper a novel compensation method for low power two-stage operational Amplifiers is
proposed. The proposed model is used 50 nm CMOS technology and employs a 50 femto …
proposed. The proposed model is used 50 nm CMOS technology and employs a 50 femto …
Yield constrained automated design algorithm for power optimized pipeline ADC
Abstract Pipeline Analog to Digital Converter (ADC) design processes include several
redesign steps to achieve the optimum solution. Hence, designers prefer to use automated …
redesign steps to achieve the optimum solution. Hence, designers prefer to use automated …
Adaptive power management in software radios using resolution adaptive analog to digital converters
D Hostetler, Y **e - … Society Annual Symposium on VLSI: New …, 2005 - ieeexplore.ieee.org
The popularity of software radios is increasing, as they have become one of the important
emerging technologies in mobile communications. One of the major challenges during …
emerging technologies in mobile communications. One of the major challenges during …
[PDF][PDF] A 10-bit 10 Msample/s pipelined ADC in 0.35 μ m CMOS technology
Based on principle of Pipeline ADC, an 8* 1-bit eight-stage 10-bit pipeline analog-to-digital
converter (ADC) is presented. Combining bootstrap circuit and bottom-plate sampling …
converter (ADC) is presented. Combining bootstrap circuit and bottom-plate sampling …