(57) ABSTRACT A suite of novel structures and methods is provided to reduce power
consumption in a wide array of electronic devices and systems. Some of these structures …

6,808 004 B2 10/2004 Kamm et a1, 7,398,497 B2 7/2008 Sato et 31. 63083994 B1 10/2004
Wang 7,402,207 B1 7/2008 Besser et a1. 6,813,750 B2 11/2004 Usami et 31 ' 7,402,872 B2 …

Some structures and methods to reduce power consumption in devices can be implemented
largely by reusing existing bulk CMOS process flows and manufacturing technology …

Related US Application Data Non-Final Office Action dated Feb. 12, 2008; US Appl. No.(63)
Continuation of application No. 12/552,243, filed on 1 1/528,031. Sep. 1, 2009, now Pat. No …

Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced
OV, compared to conven tional bulk CMOS and can allow the threshold voltage V of FETs …

WSS a plurality of transistors, each transistor in the plurality of transistors having a Substrate
terminal. In one example, the first voltage source Supplies, via the diode, the Substrate …

US7256639B1 - Systems and methods for integrated circuits comprising multiple body bias
domains - Google Patents US7256639B1 - Systems and methods for integrated circuits …

US6933744B2 - Low-leakage integrated circuits and dynamic logic circuits - Google
Patents US6933744B2 - Low-leakage integrated circuits and dynamic logic circuits …

An advanced transistor with punch through suppression includes a gate with length Lg, a
well doped to have a? rst concentration of a dopant, and a screening region positioned …

(57) ABSTRACT A semiconductor integrated circuit includes: a first MOS transistor having
one Source/drain electrode for receiving a power Supply Voltage and the other Source/drain …