We report on the process for formal concurrency modelling at Arm. An initial formal
consistency model of the Arm achitecture, written in the cat language, was published and …

We propose an axiomatic generic framework for modelling weak memory. We show how to
instantiate this framework for Sequential Consistency (SC), Total Store Order (TSO), C++ …

Exploiting today's multiprocessors requires high-performance and correct concurrent
systems code (optimising compilers, language runtimes, OS kernels, etc.), which in turn …

ARM has a relaxed memory model, previously specified in informal prose for ARMv7 and
ARMv8. Over time, and partly due to work building formal semantics for ARM concurrency, it …

We propose leakage containment models (LCMs)---novel axiomatic security contracts which
support formally reasoning about the security guarantees of programs when they run on …

In this paper we develop semantics for key aspects of the ARMv8 multiprocessor
architecture: the concurrency model and much of the 64-bit application-level instruction set …

Abstract ARM and IBM POWER multiprocessors have highly relaxed memory models: they
make use of a range of hardware optimisations that do not affect the observable behaviour …

Concurrency is pervasive and perplexing, particularly on graphics processing units (GPUs).
Current specifications of languages and hardware are inconclusive; thus programmers often …

The growing complexity of hardware optimizations employed by multiprocessors leads to
subtle distinctions among allowed and disallowed behaviors, posing challenges in …

Recent research has uncovered a broad class of security vulnerabilities in which
confidential data is leaked through programmer-observable microarchitectural state. In this …