Toward smart embedded systems: A self-aware system-on-chip (soc) perspective

N Dutt, A Jantsch, S Sarma - ACM Transactions on Embedded …, 2016 - dl.acm.org
Embedded systems must address a multitude of potentially conflicting design constraints
such as resiliency, energy, heat, cost, performance, security, etc., all in the face of highly …

Accounting for Machine Learning Prediction Errors in Design

X Du - Journal of Mechanical Design, 2024 - asmedigitalcollection.asme.org
Abstract Machine learning is gaining prominence in mechanical design, offering cost-
effective surrogate models to replace computationally expensive models. Nevertheless …

On characterizing near-threshold SRAM failures in FinFET technology

S Ganapathy, J Kalamatianos, K Kasprak… - Proceedings of the 54th …, 2017 - dl.acm.org
Adoption of near-threshold voltage (NTV) operation in SRAM-based memories has been
limited by reduced robustness resulting from marginal transistor operation that results in bit …

Parasitics-aware design of symmetric and asymmetric gate-workfunction FinFET SRAMs

AN Bhoj, NK Jha - IEEE Transactions on Very Large Scale …, 2013 - ieeexplore.ieee.org
Multigate FET technology is the most viable successor to planar CMOS technology at the 22-
nm node and beyond. Prior research on multigate SRAMs is generally confined to the …

A charge-recycling assist technique for reliable and low power SRAM design

W Choi, J Park - IEEE Transactions on Circuits and Systems I …, 2016 - ieeexplore.ieee.org
This paper presents a novel charge-recycling SRAM assist circuit to reduce the dynamic
power consumption of SRAM assist technique. By collaboratively combining the read and …

Possibility-based Sizing Method for Hybrid Electric Aircraft

ZW Thu, M Tyan, YH Choi, MI Alam, JW Lee - IEEE Access, 2025 - ieeexplore.ieee.org
At the early stage of aircraft design, the sizing process plays a critical role in determining key
parameters such as mass, geometry, and propulsion system characteristics based on design …

Statistical analysis of 6T SRAM data retention voltage under process variation

EI Vatajelu, J Figueras - 14th IEEE International Symposium on …, 2011 - ieeexplore.ieee.org
One of the main issues in scaled SRAMs is the increase in static power. A common way to
reduce the static power consumption of an SRAM array is to decrease its supply voltage …

Resiliency challenges in sub-10nm technologies

R Aitken, EH Cannon, M Pant… - 2015 IEEE 33rd VLSI …, 2015 - ieeexplore.ieee.org
Improvements in chip manufacturing technology, driven by high degree of integration due to
small device sizes and additional complex functionalities enabled by heterogeneous …

Probabilistic standard cell modeling considering non-Gaussian parameters and correlations

A Lange, C Sohrmann, R Jancke… - … , Automation & Test …, 2014 - ieeexplore.ieee.org
Variability continues to pose challenges to integrated circuit design. With statistical static
timing analysis and high-yield estimation methods, solutions to particular problems exist, but …

An analytical model for performance yield of nanoscale SRAM accounting for the sense amplifier strobe signal

JF Ryan, S Khanna, BH Calhoun - IEEE/ACM International …, 2011 - ieeexplore.ieee.org
This paper presents a model for the exact distribution of performance yield in an SRAM
using order statistics for strobed and non-strobed sense amplifier (SA) implementations …