Low-power pulse-triggered flip-flop design with conditional pulse-enhancement scheme
In this paper, a novel low-power pulse-triggered flip-flop (FF) design is presented. First, the
pulse generation control logic, an and function, is removed from the critical path to facilitate a …
pulse generation control logic, an and function, is removed from the critical path to facilitate a …
Low-power pulse-triggered flip-flop design based on a signal feed-through
JF Lin - IEEE transactions on very large scale integration (vlsi) …, 2013 - ieeexplore.ieee.org
In this brief, a low-power flip-flop (FF) design featuring an explicit type pulse-triggered
structure and a modified true single phase clock latch based on a signal feed-through …
structure and a modified true single phase clock latch based on a signal feed-through …
Low-power dual dynamic node pulsed hybrid flip-flop featuring efficient embedded logic
K Absel, L Manuel, RK Kavitha - IEEE transactions on very large …, 2012 - ieeexplore.ieee.org
In this paper, we introduce a new dual dynamic node hybrid flip-flop (DDFF) and a novel
embedded logic module (DDFF-ELM) based on DDFF. The proposed designs eliminate the …
embedded logic module (DDFF-ELM) based on DDFF. The proposed designs eliminate the …
Design and analysis of ultra‐low power 18T adaptive data track flip‐flop for high‐speed application
A Kumar Mishra, D Vaithiyanathan… - International Journal of …, 2021 - Wiley Online Library
This paper proposes a novel master slave (MS) flip‐flop design achieved by using only 18
transistors with a single‐phase clock and mixed topology. This design has lowest …
transistors with a single‐phase clock and mixed topology. This design has lowest …
Ultra-low power pulse-triggered CNTFET-based flip-flop
Reducing the power consumption and scaling the devices are the important concerns of
today's electronics. Flip-Flop (FF) is one of the basic elements in electronic devices. Thus …
today's electronics. Flip-Flop (FF) is one of the basic elements in electronic devices. Thus …
A novel design for ultra-low power pulse-triggered D-Flip-Flop with optimized leakage power
The power efficiency and reducing the layout area are two main concerns in D-Flip-Flops (D-
FF) design. In this paper, a novel architecture is presented for the pulse-triggered D-FF in the …
FF) design. In this paper, a novel architecture is presented for the pulse-triggered D-FF in the …
A highly efficient conditional feedthrough pulsed flip-flop for high-speed applications
D Pan, C Ma, L Cheng, H Min - IEEE Transactions on Very …, 2019 - ieeexplore.ieee.org
A novel type of highly efficient conditional feedthrough pulse-triggered flip-flop (P-FF) is
proposed and demonstrated. The data-to-output (D-to-Q) delay in this circuit was highly …
proposed and demonstrated. The data-to-output (D-to-Q) delay in this circuit was highly …
Self-timed pulsed latch for low-voltage operation with reduced hold time
H Jeong, J Park, SC Song… - IEEE Journal of Solid …, 2019 - ieeexplore.ieee.org
A self-timed pulsed latch (STPL) is proposed for low VDD operation. By comparing input and
output, the transparency window is adaptively generated in STPL, which resolves the hold …
output, the transparency window is adaptively generated in STPL, which resolves the hold …
Power consumption and delay comparison of a modified tcff with existing ff implemented using finfet and load test circuit analysis
D Vaithiyanathan, AK Mishra… - 2021 IEEE Madras …, 2021 - ieeexplore.ieee.org
In this paper a single phase clock flip-flop has been introduced. This is a modified version of
topologically compressed flip-flop. It consist of 19 transistors which is two transistor less than …
topologically compressed flip-flop. It consist of 19 transistors which is two transistor less than …
N-Parallel Paths based D-Latch for High Speed Applications
R Rakhi, RK Siddharth, KG Shreeharsha… - IEEE …, 2024 - ieeexplore.ieee.org
In this paper, a parallel discharge path-based D-latch architecture is proposed to enhance
its speed performance compared to the conventional D-latch. The improvement is achieved …
its speed performance compared to the conventional D-latch. The improvement is achieved …