Single event upset: An embedded tutorial
With the continuous downscaling of CMOS technologies, the reliability has become a major
bottleneck in the evolution of the next generation systems. Technology trends such as …
bottleneck in the evolution of the next generation systems. Technology trends such as …
A logic-level model for/spl alpha/-particle hits in CMOS circuits
H Cha, JH Patel - … of 1993 IEEE International Conference on …, 1993 - ieeexplore.ieee.org
Systems designed for reliability must be validated through simulations. However, traditional
SPICE like simulators or even mixed-mode simulators are too slow for the task of simulating …
SPICE like simulators or even mixed-mode simulators are too slow for the task of simulating …
A gate-level simulation environment for alpha-particle-induced transient faults
H Cha, EM Rudnick, JH Patel, RK Iyer… - IEEE Transactions on …, 1996 - ieeexplore.ieee.org
Mixed analog and digital mode simulators have been available for accurate/spl alpha/-
particle-induced transient fault simulation. However, they are not fast enough to simulate a …
particle-induced transient fault simulation. However, they are not fast enough to simulate a …
FOCUS: An experimental environment for fault sensitivity analysis
GS Choi, RK Iyer - IEEE Transactions on Computers, 1992 - computer.org
FOCUS, a simulation environment for conducting fault-sensitivity analysis of chip-level
designs, is described. The environment can be used to evaluate alternative design tactics at …
designs, is described. The environment can be used to evaluate alternative design tactics at …
High robust and cost effective double node upset tolerant latch design for nanoscale CMOS technology
H Li, L **ao, J Li, C Qi - Microelectronics Reliability, 2019 - Elsevier
In this paper, we propose a novel high reliability and low cost DNU (Double Node Upset)
tolerant latch, HRCE (High Robust and Cost Effective) latch, for nanoscale CMOS …
tolerant latch, HRCE (High Robust and Cost Effective) latch, for nanoscale CMOS …
[PDF][PDF] Fast timing simulation of transient faults in digital circuits
A Dharchoudhury, SM Kang, H Cha… - Proceedings of The …, 1994 - websrv.cecs.uci.edu
Transient fault simulation is an important verification activity for circuits used in critical
applications since such faults account for over 80% of all system failures. This paper …
applications since such faults account for over 80% of all system failures. This paper …
MIMD synchronization on SIMT architectures
In the single-instruction multiple-threads (SIMT) execution model, small groups of scalar
threads operate in lockstep. Within each group, current SIMT hardware implementations …
threads operate in lockstep. Within each group, current SIMT hardware implementations …
Reliable and high performance asymmetric FinFET SRAM cell using back-gate control
As the technology scales down, the performance characteristics are degraded and the
reliability of digital circuits against soft error and aging effects are reduced. In this paper, we …
reliability of digital circuits against soft error and aging effects are reduced. In this paper, we …
Soft error rate determination for nanometer CMOS VLSI logic
Nanometer CMOS VLSI circuits are highly sensitive to soft errors due to environmental
causes such as cosmic radiation and charged particles. These phenomena, also known as …
causes such as cosmic radiation and charged particles. These phenomena, also known as …
Design and analysis of single-event tolerant slave latches for enhanced scan delay testing
The last few years have seen the development and fabrication of nanoscale circuits at high
density and low power. Following a single-event upset (SEU), so-called soft errors due to …
density and low power. Following a single-event upset (SEU), so-called soft errors due to …