Low-frequency noise in downscaled silicon transistors: Trends, theory and practice

O Marinov, MJ Deen, JA Jiménez-Tejada - Physics Reports, 2022 - Elsevier
By the continuing downscaling of sub-micron transistors in the range of few to sub-
decananometers, we focus on the increasing relative level of the low-frequency noise in …

TCAD assessment of gate electrode workfunction engineered recessed channel (GEWE-RC) MOSFET and its multilayered gate architecture—part I: hot-carrier …

R Chaujar, R Kaur, M Saxena, M Gupta… - IEEE transactions on …, 2008 - ieeexplore.ieee.org
This paper discusses a hot-carrier-reliability assessment, using ATLAS device simulation
software, of a gate electrode workfunction engineered recessed channel (GEWE-RC) …

On the oxide trap density and profiles of 1-nm EOT metal-gate last CMOS transistors assessed by low-frequency noise

E Simoen, A Veloso, Y Higuchi… - IEEE transactions on …, 2013 - ieeexplore.ieee.org
The low-frequency noise behavior of replacement metal gate high-k/metal-gate MOSFETs
with an equivalent oxide thickness of the SiO 2/HfO 2 bilayer in the range~ 1 nm has been …

On the 1/f noise of triple-gate field-effect transistors with high-k gate dielectric

N Lukyanchikova, N Garbar, V Kudina… - Applied Physics …, 2009 - pubs.aip.org
The low-frequency noise of triple-gate fin field-effect transistors (finFETs) fabricated on
silicon-on-insulator (SOI) substrates, with HfO 2 or HfSiON gate stacks has been studied. In …

Characteristics of high-quality HfSiON gate dielectric prepared by physical vapour deposition

X Gao-Bo, X Qiu-**a - Chinese Physics B, 2009 - iopscience.iop.org
This paper presents a method using simple physical vapour deposition to form high-quality
hafnium silicon oxynitride (HfSiON) on ultrathin SiO 2 buffer layer. The gate dielectric with 10 …

Effect of rotation, gate-dielectric and SEG on the noise behavior of advanced SOI MuGFETs

S Put, H Mehta, N Collaert, M Van Uffelen, P Leroux… - Solid-state …, 2010 - Elsevier
In this work the influence of Selective Epitaxial Growth (SEG), high-k gate-dielectric and
rotation of the channel on the low frequency (LF)-noise is investigated. The carrier number …

[書籍][B] Variation aware analog and mixed-signal circuit design in emerging multi-gate CMOS technologies

M Fulde - 2009 - books.google.com
Since scaling of CMOS is reaching the nanometer area serious limitations enforce the
introduction of novel materials, device architectures and device concepts. Multi-gate devices …

Analog design challenges and trade-offs using emerging materials and devices

M Fulde, A Mercha, C Gustin, B Parvais… - … 2007-37th European …, 2007 - ieeexplore.ieee.org
Analog device figures-of-merit change significantly with the introduction of advanced
materials and devices such as high-k or multiple-gate FETs. Measurements show enhanced …

Border-Trap Characterization in High- Strained-Si MOSFETs

D Maji, SP Duttagupta, VR Rao… - IEEE electron device …, 2007 - ieeexplore.ieee.org
In this letter, we focus on the border-trap characterization of TaN/HfO 2/Si and TaN/HfO
2/strained-Si/Si 0.8 Ge 0.2 n-channel MOSFET devices. The equivalent oxide thickness for …

Heat stress exposing performance of deep-nano HK/MG nMOSFETs using DPN or PDA treatment

SJ Wang, MC Wang, SY Chen, WH Lan… - Microelectronics …, 2015 - Elsevier
Decoupled plasma nitridation (DPN) or post-deposition annealing (PDA) process after high-
k (HK) deposition to repair the bulk traps or the oxygen vacancy in gate dielectric is an …