This paper proposes an architecture of a virtual channel router for an on-chip network. The
router has simple dynamic arbitration which is deterministic and fair. We show that the size …

According to the granularity of configuration, reconfigurable systems are classified in two
categories, which are the fine-and coarse-grain ones. The purpose of this chapter is to study …

Mobile wireless terminals tend to become multimode wireless communication devices.
Furthermore, these devices become adaptive. Heterogeneous reconfigurable hardware …

This paper presents an on-chip network for a runtime reconfigurable system-on-chip. The
network uses packet-switching with virtual channels. It can provide guaranteed services as …

This paper presents a new methodology for the synthesis of high performance flexible
datapaths, targeting computationally intensive digital signal processing kernels of …

Future mobile communication systems have to be flexible while adapting to environmental
conditions and user demands. These systems also have to be energy-efficient as they are …

This paper investigates the impact of the local and global register file architecture on a
reconfigurable system based on the ADRES architecture. The register files consume a …

With the advance of semiconductor technology, global on-chip wiring is becoming a limiting
factor for the overall performance of large System-on-Chip (SoC) designs. In this thesis we …

A homogeneous architecture made of an array of so-called NPUs (network processing units)
is presented in this paper. Those NPUs are endowed with elementary processing and …

Application accelerators are predominantly ASICs. The cost of ASIC solutions are order of
magnitudes higher than programmable processing cores. Despite this, ASIC solutions are …