2011-12-06 Assigned to MONOLITHIC 3D INC. reassignment MONOLITHIC 3D INC.
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …

BACKGROUND The present invention relates to programmable structured arrays for
semiconductor integrated circuits. Traditionally, application specific integrated circuit (ASIC) …

An integrated circuit fabricated by a mask set including a mask to generate a metal pattern
defined by CAD software, the metal pattern generation method including: reading a binary …

BACKGROUND The present invention relates to multi-dimensional inte grated circuits. More
specifically it relates to ROM program mable 3D ICs. Traditionally, integrated circuit (IC) …

4,609,986 A 9, 1986 Hartmann et al. 4,706,216 A 11/1987 Carter 4,761,768 A 8, 1988
Turner et al. 4,831,573 A 5/1989 Norman 4,864,161 A 9, 1989 Norman et al. 4,870,302 A 9 …

It is generally acknowledged that nanoelectronics will eventually replace traditional silicon
CMOS in high-performance integrated circuits. To that end, considerable investments are …

12, 1997 7, 1998 8, 1998 11, 1998 12, 1998 3, 1999 8, 1999 9, 1999 9, 1999 12, 1999 1,
2000 8, 2000 10, 2000 10, 2000 2, 2001 6, 2001 T/2001 T/2001 8, 2001 8, 2001 12, 2001 …

(57) ABSTRACT A three-dimensional semiconductor device, comprising: a first module layer
having a plurality of circuit blocks; and a second module layer positioned substantially …

US10515981B2 - Multilevel semiconductor device and structure with memory - Google
Patents US10515981B2 - Multilevel semiconductor device and structure with memory …

(57) ABSTRACT A three dimensional semiconductor device, comprising: a Substrate
including a plurality of circuits; a plurality of pads, each pad coupled to a said circuit; and a …