[PDF][PDF] ADKNN fostered BIST with Namib Beetle optimization algorithm espoused BISR for SoC-based devices
Redundancy analysis is a widely used method in fault-tolerant memory systems, and it is
essential for large-size memories. In current security operations centers (SoCs), memory …
essential for large-size memories. In current security operations centers (SoCs), memory …
IFCN-BIASN Based Built-in Test Signal State Recognition for Heavy-duty Gas Turbine Controller
C Huang, Y Yang - IEEE Transactions on Instrumentation and …, 2024 - ieeexplore.ieee.org
Built-in test (BIT) technology is gradually employed in predictive maintenance of equipment
state. However, the accurate signal state judgment of conventional BIT (CBIT) is affected by …
state. However, the accurate signal state judgment of conventional BIT (CBIT) is affected by …
A Scan-Chain Based Built-In Self-Test for ILV in Monolithic 3D ICs
T Chen, R Ding, J Liu, X Yuan, Y Lu… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
In comparison with through-silicon vias (TSVs) used in 3-D integrated circuits (3D ICs),
nanoscale interlayer via (ILV) employed in monolithic 3D ICs offers higher integration …
nanoscale interlayer via (ILV) employed in monolithic 3D ICs offers higher integration …
Research on Multi-Fault Testing Method for MIV Based on Grid Search and Random Forest
Y Shang, L Geng, C Li, Z Song… - IEEE Transactions on …, 2025 - ieeexplore.ieee.org
With the fast development trend of highly integrated electronic products, as the key
technology of three-dimensional (3D) interconnect circuits, the research on Monolithic Inter …
technology of three-dimensional (3D) interconnect circuits, the research on Monolithic Inter …
An MIV Fault Diagnosis Method Based on Signal Transmission Performance Analysis
Z **ao, L Du, Z Yang, C Liu, Y Yu - IEEE Transactions on Very …, 2024 - ieeexplore.ieee.org
Monolithic inter-tier vias (MIVs) in monolithic 3-D integrated circuits (M3D ICs) enables
massive vertical integration. However, MIVs are more susceptible to defects due to high …
massive vertical integration. However, MIVs are more susceptible to defects due to high …
A Post-Bond ILV Test Method in Monolithic 3-D ICs
X Fang, X Zhao - IEEE Transactions on Very Large Scale …, 2024 - ieeexplore.ieee.org
Monolithic 3-D (M3D) integrated circuits (ICs) have the potential to achieve significantly
higher device density compared with conventional ICs. The implementation of nanoscale …
higher device density compared with conventional ICs. The implementation of nanoscale …
Design-for-Test Solutions for 3D Integrated Circuits
As Moore's Law approaches its limits, 3-D integrated circuits (ICs) have emerged as
promising alternatives to conventional scaling methodologies. However, the benefits of 3-D …
promising alternatives to conventional scaling methodologies. However, the benefits of 3-D …
A Clustering-BIST Design for Inter-Layer Vias in 3D ICs Based on Walking Pattern Approach
 In the realm of 3D monolithic integrated circuits,  inter-layer vias are prone to defects
during fabrication, assembly, Â and operation that necessitate robust Built-In Self-Test …
during fabrication, assembly, Â and operation that necessitate robust Built-In Self-Test …
Responsive Tuning Strategies for VLSI Test and Diagnosis
M Joshi, K Suneetha, N Saraswat - … International Conference on …, 2024 - ieeexplore.ieee.org
This technical abstract explores the application of responsive tuning techniques for VLSI
(Very Large Scale Integration) check and analysis. In particular, the focal point of the paper …
(Very Large Scale Integration) check and analysis. In particular, the focal point of the paper …