Multipliers in a digital processor remains as a core of mathematical computing paradigm. In
ancient times Vedic mathematicians developed basic multiplication algorithms. This study …

As floating point architecture is very hot topic for researchers so challenges are always there
to design the efficient Floating point architecture. Out of other operations, Floating point …

In this paper, an 8-bit Vedic multiplier is designed. The performance of the system basically
works better if the performance of the multiplier is good. In today's digital time, Multiplier is …

Most of the DSP applications suffer from the stringent power dissipation constraints and
demand the high speed, low power and low area multiplier for the VLSI circuits to give better …

This research presents a comprehensive differential analysis of 32-bit Vedic multipliers
employing distinct adder types namely, RCA, CLA, and CSA. The underlying Vedic …

In computing architecture, ALU plays a major role. Many promising applications are possible
with ATMEGA microcontroller. ALU is a part of these microcontrollers. The performance of …

In wireless communication systems like mobile or satellite network a specified band is
allotted. Each network has its own allotted spectrum for safe and secure communication …

In wide communication network, signals are transferred and receive. In case of wireless
systems transferring a signal over a wide spectrum and providing a security to such signal is …

This paper proposes a possible solution to reducing power consumption on CMOS multiplier
circuits. Specifically, this paper looks into one of sixteen of the ancient sutras in Vedic …

The paper proposes an approach means “antiquated Vedic mathematics” for high rate
multiplier based on sixteen sutras. In this paper, we manipulated Urdhva-Triyagbhyam sutra …