A mechanistic model for out-of-order superscalar processors is developed and then applied
to the study of microarchitecture resource scaling. The model divides execution time into …

Growing on-chip wire delays will cause many future microarchitectures to be distributed, in
which hardware resources within a single processor become nodes on one or more …

Today's computers employ significant heterogeneity to meet performance targets at
manageable power. In adopting increased compute specialization, however, the relative …

A multiprocessor's memory consistency model imposes ordering constraints among loads,
stores, atomic operations, and memory fences. Even for consistency models that relax …

We've seen the quick adoption of GPUs as general-purpose computing engines in recent
years, fueled by high computational throughput and energy efficiency. There is heavier …

Modern processors employ large structures (IQ, LSQ, register file, etc.) to expose instruction-
level parallelism (ILP) and memory-level parallelism (MLP). These resources are typically …

In Total Store Order memory consistency (TSO), loads can be speculatively reordered to
improve performance. If a load-load reordering is seen by other cores, speculative loads …

Historically, advances in integrated circuit technology have driven improvements in
processor microarchitecture and led to todays microprocessors with sophisticated pipelines …

Growing concerns about power have revived interest in in-order pipelines. In-order pipelines
sacrifice single-thread performance. Specifically, they do not allow execution to flow freely …

In today's computers, heterogeneous processing is used to meet performance targets at
manageable power. In adopting increased compute specialization, however, the relative …