Chip design with machine learning: a survey from algorithm perspective
Chip design with machine learning (ML) has been widely explored to achieve better
designs, lower runtime costs, and no human-in-the-loop process. However, with tons of …
designs, lower runtime costs, and no human-in-the-loop process. However, with tons of …
Large circuit models: opportunities and challenges
Within the electronic design automation (EDA) domain, artificial intelligence (AI)-driven
solutions have emerged as formidable tools, yet they typically augment rather than redefine …
solutions have emerged as formidable tools, yet they typically augment rather than redefine …
Graph neural networks: A powerful and versatile tool for advancing design, reliability, and security of ICs
Graph neural networks (GNNs) have pushed the state-of-the-art (SOTA) for performance in
learning and predicting on large-scale data present in social networks, biology, etc. Since …
learning and predicting on large-scale data present in social networks, biology, etc. Since …
Why are graph neural networks effective for eda problems?
In this paper, we discuss the source of effectiveness of Graph Neural Networks (GNNs) in
EDA, particularly in the VLSI design automation domain. We argue that the effectiveness …
EDA, particularly in the VLSI design automation domain. We argue that the effectiveness …
The dawn of ai-native eda: Promises and challenges of large circuit models
Within the Electronic Design Automation (EDA) domain, AI-driven solutions have emerged
as formidable tools, yet they typically augment rather than redefine existing methodologies …
as formidable tools, yet they typically augment rather than redefine existing methodologies …
A survey and perspective on artificial intelligence for security-aware electronic design automation
Artificial intelligence (AI) and machine learning (ML) techniques have been increasingly
used in several fields to improve performance and the level of automation. In recent years …
used in several fields to improve performance and the level of automation. In recent years …
Transsizer: A novel transformer-based fast gate sizer
Gate sizing is a fundamental netlist optimization move and researchers have used
supervised learning-based models in gate sizers. Recently, Reinforcement Learning (RL) …
supervised learning-based models in gate sizers. Recently, Reinforcement Learning (RL) …
Agd: A learning-based optimization framework for eda and its application to gate sizing
P Pham, J Chung - 2023 60th ACM/IEEE Design Automation …, 2023 - ieeexplore.ieee.org
In electronic design automation (EDA), most simulation models are not differentiable, and
many design choices are discrete. As a result, greedy optimization methods based on …
many design choices are discrete. As a result, greedy optimization methods based on …
Heterogeneous graph neural network-based imitation learning for gate sizing acceleration
Gate Sizing is an important step in logic synthesis, where the cells are resized to optimize
metrics such as area, timing, power, leakage, etc. In this work, we consider the gate sizing …
metrics such as area, timing, power, leakage, etc. In this work, we consider the gate sizing …
On advancing physical design using graph neural networks
As modern Physical Design (PD) algorithms and methodologies evolve into the post-Moore
era with the aid of machine learning, Graph Neural Networks (GNNs) are becoming …
era with the aid of machine learning, Graph Neural Networks (GNNs) are becoming …