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Energy efficient design techniques in next‐generation wireless communication networks: emerging trends and future directions
The projected rise in wireless communication traffic has necessitated the advancement of
energy‐efficient (EE) techniques for the design of wireless communication systems, given …
energy‐efficient (EE) techniques for the design of wireless communication systems, given …
An 80-tile sub-100-w teraflops processor in 65-nm cmos
This paper describes an integrated network-on-chip architecture containing 80 tiles
arranged as an 8x10 2-D array of floating-point cores and packet-switched routers, both …
arranged as an 8x10 2-D array of floating-point cores and packet-switched routers, both …
High-performance and low-power conditional discharge flip-flop
In this paper, high-performance flip-flops are analyzed and classified into two categories: the
conditional precharge and the conditional capture technologies. This classification is based …
conditional precharge and the conditional capture technologies. This classification is based …
Methods for true energy-performance optimization
This paper presents methods for efficient energy-performance optimization at the circuit and
micro-architectural levels. The optimal balance between energy and performance is …
micro-architectural levels. The optimal balance between energy and performance is …
Level conversion for dual-supply systems
Dual-supply voltage design using a clustered voltage scaling (CVS) scheme is an effective
approach to reduce chip power. The optimal CVS design relies on a level converter (LC) …
approach to reduce chip power. The optimal CVS design relies on a level converter (LC) …
[کتاب][B] Low-power electronics design
C Piguet - 2018 - books.google.com
The power consumption of integrated circuits is one of the most problematic considerations
affecting the design of high-performance chips and portable devices. The study of power …
affecting the design of high-performance chips and portable devices. The study of power …
A partially static high frequency 18t hybrid topological flip-flop design for low power application
In this brief, an extremely low power true clocking flip-flop is proposed using eighteen
transistors only. The flip-flop is a synchronous bistable element that stores single-bit …
transistors only. The flip-flop is a synchronous bistable element that stores single-bit …
Variations in nanometer CMOS flip-flops: Part I—Impact of process variations on timing
In this paper, split into Part I and II, the impact of variations on single-edge triggered flip-flops
(FFs) is comparatively evaluated across a wide range of state-of-the-art topologies. The …
(FFs) is comparatively evaluated across a wide range of state-of-the-art topologies. The …
Analysis and comparison in the energy-delay-area domain of nanometer CMOS flip-flops: Part I—Methodology and design strategies
In this paper (split into Parts I and II), an extensive comparison of existing flip-flop (FF)
classes and topologies is carried out. In contrast to previous works, analysis explicitly …
classes and topologies is carried out. In contrast to previous works, analysis explicitly …
Low-power 19-transistor true single-phase clocking flip-flop design based on logic structure reduction schemes
In this paper, an ultralow-power true single-phase clocking flip-flop (FF) design achieved
using only 19 transistors is proposed. The design follows a master-slave-type logic structure …
using only 19 transistors is proposed. The design follows a master-slave-type logic structure …