Semiconductor device and manufacturing method thereof
CC Cheng, HL Chiang, C Tzu-Chiang… - US Patent …, 2021 - Google Patents
In a method of manufacturing a semiconductor device, a fin structure, in which first
semiconductor layers and second semiconductor layers are alternately stacked, is formed …
semiconductor layers and second semiconductor layers are alternately stacked, is formed …
Semiconductor device and manufacturing method thereof
CC Cheng, HL Chiang, C Tzu-Chiang… - US Patent …, 2021 - Google Patents
In a method of manufacturing a semiconductor device, a fin structure, in which first
semiconductor layers and second semiconductor layers are alternately stacked, is formed …
semiconductor layers and second semiconductor layers are alternately stacked, is formed …
Selective inner spacer implementations
A semiconductor device according to the present disclosure includes first gate-all-around
(GAA) devices in a first device area and second GAA devices in a second device area. Each …
(GAA) devices in a first device area and second GAA devices in a second device area. Each …
Wrap around contact for nanosheet source drain epitaxy
9,570,609 B2* 2/2017 Obradovic HO1L 29/78681 9,842,914 B1 12/2017 Yeung et al.
9,847,390 B1 12/2017 **e et al. 9,954,058 B1* 4/2018 Mochizuki HO1L 29/42392 …
9,847,390 B1 12/2017 **e et al. 9,954,058 B1* 4/2018 Mochizuki HO1L 29/42392 …
Gate-all-around devices with optimized gate spacers and gate end dielectric
JJ Liaw - US Patent 11,581,414, 2023 - Google Patents
US11581414B2 - Gate-all-around devices with optimized gate spacers and gate end dielectric
- Google Patents US11581414B2 - Gate-all-around devices with optimized gate spacers and …
- Google Patents US11581414B2 - Gate-all-around devices with optimized gate spacers and …
Method of manufacturing a semiconductor device and a semiconductor device
S Kuan, SB More, LIN Chien, CH Lee… - US Patent …, 2024 - Google Patents
In a method of manufacturing a semiconductor device, a fin structure in which first
semiconductor layers and second semiconductor layers are alternately stacked is formed, a …
semiconductor layers and second semiconductor layers are alternately stacked is formed, a …
Inner spacer features for multi-gate transistors
BF Wu, CH Yu, CP Lin - US Patent 11,289,584, 2022 - Google Patents
(57) ABSTRACT A semiconductor device according to the present disclosure includes a
channel member including a first connection portion, a second connection portion and a …
channel member including a first connection portion, a second connection portion and a …
Semiconductor structure and method for forming the same
KH Fung - US Patent 11,756,997, 2023 - Google Patents
A semiconductor structure is provided. The semiconductor structure includes a plurality of
nanostructures vertically stacked and separated from one another. The semiconductor …
nanostructures vertically stacked and separated from one another. The semiconductor …
Semiconductor device
KO Myung-Dong, WC Shin, SJ Jeong - US Patent 11,978,770, 2024 - Google Patents
A semiconductor device includes a substrate, an active pattern extending in a first direction
on the substrate, first and second nanosheets stacked on the active pattern to be spaced …
on the substrate, first and second nanosheets stacked on the active pattern to be spaced …
Semiconductor device
T Yabe, M Yano - US Patent 10,847,615, 2020 - Google Patents
A semiconductor device includes a substrate; a first semiconductor layer above the
substrate, a second semiconductor layer between the substrate and the first semiconductor …
substrate, a second semiconductor layer between the substrate and the first semiconductor …