Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes
In this paper, for the first time, we have investigated the DC, analog/RF, and linearity metrics
of asymmetric spacer junctionless (JL) Gate-All-Around (GAA) vertically stacked nanowire …
of asymmetric spacer junctionless (JL) Gate-All-Around (GAA) vertically stacked nanowire …
Dual-material dual-oxide double-gate TFET for improvement in DC characteristics, analog/RF and linearity performance
To overcome the problem of fabrication complexity and to reducei the cost of microelectronic
devices, a new concept of dual-material control gate with dual-oxide tunnel field-effect …
devices, a new concept of dual-material control gate with dual-oxide tunnel field-effect …
Improving the electrical characteristics of nanoscale triple-gate junctionless FinFET using gate oxide engineering
NB Bousari, MK Anvarifard, S Haji-Nasiri - AEU-International Journal of …, 2019 - Elsevier
This paper is about the compared performance investigation of various structures of Hetero-
Dielectric (HD) triple-gate FinFETs with different gate oxides in terms of Double Hetero Gate …
Dielectric (HD) triple-gate FinFETs with different gate oxides in terms of Double Hetero Gate …
DC and RF/analog performances of split source horizontal pocket and hetero stack TFETs considering interface trap charges: a simulation study
This work investigates the impact of different types of interface trap charges (ITCs) on
electrical parameters of split source horizontal pocket Z shape TFET (ZHP-TFET) and Hetero …
electrical parameters of split source horizontal pocket Z shape TFET (ZHP-TFET) and Hetero …
Comparative analysis of the quantum FinFET and trigate FinFET based on modeling and simulation
A comparative analysis of the trigate fin-shaped field-effect transistor (FinFET) and quantum
FinFET (QFinFET) is carried out by using density gradient quantization models in the …
FinFET (QFinFET) is carried out by using density gradient quantization models in the …
Impact of work function variation for enhanced electrostatic control with suppressed ambipolar behavior for dual gate L-TFET
The favorable electrostatic potential and tunneling underneath the overall gate region, which
prevents legitimate source to drain tunneling, controllability over the gate is assisted in …
prevents legitimate source to drain tunneling, controllability over the gate is assisted in …
Improved Drain Current Characteristics of HfO2/SiO2 Dual Material Dual Gate Extension on Drain Side-TFET
B Balaji, K Srinivasa Rao, K Girija Sravani… - Silicon, 2022 - Springer
Abstract We Proposed Dual Material Dual Gate Extension on Drain side TFET (DMDGED-
TFET) and have analyzed, confirmed Performance characteristics in 10 nm technology. The …
TFET) and have analyzed, confirmed Performance characteristics in 10 nm technology. The …
Reduction of corner effect in ZG-ES-TFET for improved electrical performance and its reliability analysis in the presence of traps
In this paper, various electrical parameters of a Z-shaped gate elevated source TFET (ZG-ES-
TFET) in the presence of interface traps are investigated. The placement of Z-shaped gate …
TFET) in the presence of interface traps are investigated. The placement of Z-shaped gate …
Vertical tunneling FET with Ge/Si do**-less heterojunction, a high-performance switch for digital applications
A vertical tunneling field effect transistor composed of a do**-less tunneling heterojunction
and an n+-drain is presented in this paper. Two highly-doped p+ silicon layers are devised …
and an n+-drain is presented in this paper. Two highly-doped p+ silicon layers are devised …
DC and RF/analog parameters in Ge‐source split drain‐ZHP‐TFET: drain and pocket engineering technique
In this article, a Ge‐source is employed in split drain Z‐shaped line TFET structure (SD‐ZHP‐
TFET) and named as Ge‐source SD‐ZHP‐TFET. The presence of split drain increases the …
TFET) and named as Ge‐source SD‐ZHP‐TFET. The presence of split drain increases the …