OpenPiton: An open source manycore research framework

J Balkind, M McKeown, Y Fu, T Nguyen, Y Zhou… - ACM SIGPLAN …, 2016 - dl.acm.org
Industry is building larger, more complex, manycore processors on the back of strong
institutional knowledge, but academic projects face difficulties in replicating that scale. To …

[PDF][PDF] Power and Energy Characterization of an Open Source 25-Core Manycore Processor.

M McKeown, A Lavrov, M Shahrad, PJ Jackson, Y Fu… - HPCA, 2018 - princeton.edu
The end of Dennard's scaling and the looming power wall have made power and energy
primary design goals for modern processors. Further, new applications such as cloud …

Piton: A manycore processor for multitenant clouds

M McKeown, Y Fu, T Nguyen, Y Zhou, J Balkind… - Ieee …, 2017 - ieeexplore.ieee.org
The shared cloud-based computing paradigm has experienced enormous growth.
Multitenant clouds are conventionally built atop datacenters that utilize commodity hardware …

OpenPiton at 5: A nexus for open and agile hardware design

J Balkind, TJ Chang, PJ Jackson, G Tziantzioulis… - IEEE Micro, 2020 - ieeexplore.ieee.org
For five years, OpenPiton has provided hardware designs, build and verification scripts, and
other infrastructure to enable efficient, detailed research into manycores and systems-on …

Dynamic inter-thread vectorization architecture: extracting DLP from TLP

S Kalathingal, C Collange, BN Swamy… - … Architecture and High …, 2016 - ieeexplore.ieee.org
Threads of Single-Program Multiple-Data (SPMD) applications often execute the same
instructions on different data. We propose the Dynamic Inter-Thread Vectorization …

MORC: A manycore-oriented compressed cache

TM Nguyen, D Wentzlaff - … of the 48th International Symposium on …, 2015 - dl.acm.org
Cache compression has largely focused on improving single-stream application
performance. In contrast, this work proposes utilizing cache compression to improve …

Big. VLITTLE: On-demand data-parallel acceleration for mobile systems on chip

T Ta, K Al-Hawaj, N Cebry, Y Ou, E Hall… - 2022 55th IEEE/ACM …, 2022 - ieeexplore.ieee.org
Single-ISA heterogeneous multi-core architectures offer a compelling high-performance and
high-efficiency solution to executing task-parallel workloads in mobile systems on chip …

SIMT-X: Extending single-instruction multi-threading to out-of-order cores

A Tino, C Collange, A Seznec - ACM Transactions on Architecture and …, 2020 - dl.acm.org
This work introduces Single Instruction Multi-Thread Express (SIMT-X), a general-purpose
Central Processing Unit (CPU) microarchitecture that enables Graphics Processing Units …

Utilizing Subword Serialization and Parallelism to Design Efficient High-Performance Processors

PJ Jackson - 2024 - search.proquest.com
Since the first digital computers, architects have exploited transistor scaling to drive
innovation. Decreasing transistor sizes, and subsequently increasing transistor budgets, has …

[LIVRE][B] Open Source Platforms for Enabling Full-Stack Hardware-Software Research

JM Balkind - 2022 - search.proquest.com
Hardware-software research routinely starts with modelling. High-level models can capture
much of the desired system behaviour needed to begin evaluating architectural research …