Transient faults in logic circuits are becoming an important reliability concern for future
technology nodes. Radiation-induced faults have received significant attention in recent …

In this paper, we present a very fast and accurate technique to estimate the soft error rate of
digital circuits in the presence of Multiple Event Transients (METs). In the proposed …

This paper proposes a general method for the design of multiple node upset (MNU)-tolerant
latches. First, two double node upset (DNU)-tolerant latches and one triple node upset …

Due to the continuous technology scaling, soft error becomes a major reliability issue at
nanoscale technologies. Single or multiple event transients at low levels can result in …

Soft errors in combinational and sequential elements of digital circuits are an increasing
concern as a result of technology scaling. Several techniques for gate and latch hardening …

Fast, accurate, and detailed Soft Error Rate (SER) estimation of digital circuits is essential for
cost-efficient reliable design. A major step to accurately estimate a circuit SER is the …

Hardening a circuit against soft errors should be performed in early design steps before the
circuit is laid out. A viable approach to achieve soft error rate (SER) reduction at a …

Due to continuous CMOS technology downscaling, Integrated Circuits (ICs) have become
more susceptible to radiation-induced hazards such as soft errors. Thus, to design radiation …

Integrated circuits are getting increasingly vulnerable to soft errors; as a consequence, soft
error rate (SER) estimation has become an important and very challenging goal. In this work …

Selecting the ideal trade-off between reliability and cost associated with a fault tolerant
architecture generally involves an extensive design space exploration. Employing state-of …