Machine Learning-Based Power Analysis
S Shenoy, M Madhushankara… - Control and Information …, 2024 - books.google.com
Reduced Instruction Set Computing version 5 (RISC-V) is an open-source archi-tecture, a
popular choice between various integrated circuit designers. Choosing an instruction set …
popular choice between various integrated circuit designers. Choosing an instruction set …
Machine Learning-Based Power Analysis of RISC-V Processor
S Shenoy, M Madhushankara, N Sampathila… - National Conference on …, 2023 - Springer
The reduced instruction set computer, instruction set architecture, is a growingly well-liked
development environment for both hardware and software. In this study, we investigate the …
development environment for both hardware and software. In this study, we investigate the …
RISC-V core optimization in 22nm FD-SOI technology
M Doblas Font - 2021 - upcommons.upc.edu
The thesis aims to design and implement an in-order core named Sargantana using the
open RISC-V Instruction Set Architecture (ISA). Sargantana targets to improve the in-order 5 …
open RISC-V Instruction Set Architecture (ISA). Sargantana targets to improve the in-order 5 …
Task scheduling sensitivity to L1 cache settings on an area-constrained 32-core RISC-V processor
High-performance applications are highly sensitive to memory performance characteristics.
While programs with comparatively low memory-to-computation ratio are less likely to be …
While programs with comparatively low memory-to-computation ratio are less likely to be …