Sub-terahertz channel sounder: Review and future challenges

Y Lyu, P Kyösti, W Fan - China Communications, 2023 - ieeexplore.ieee.org
Due to the large amount of unused and unexplored spectrum resources, the so-called sub-
Terahertz (sub-THz) frequency bands from 100 to 300 GHz are seen as promising bands for …

A low-power SiGe BiCMOS 190-GHz transceiver chipset with demonstrated data rates up to 50 Gbit/s using on-chip antennas

D Fritsche, P Stärke, C Carta… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
This paper presents a 190-GHz direct conversion transceiver (TRX) chipset with on-chip
antennas implemented in a 130-nm SiGe BiCMOS technology for short-distance high-data …

Architecture and advanced electronics pathways toward highly adaptive energy-efficient computing

GP Fettweis, M Dör**haus, J Castrillon… - Proceedings of the …, 2018 - ieeexplore.ieee.org
With the explosion of the number of compute nodes, the bottleneck of future computing
systems lies in the network architecture connecting the nodes. Addressing the bottleneck …

A 1.38-mW 7-bit 1.7-GS/s single-channel loop-unrolled SAR ADC in 22-nm FD-SOI with 8.85 fJ/Conv.-step for GHz mobile communication and radar systems

S Buhr, CD Matthus, MM Khafaji… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
A 7-bit single-channel loop-unrolled successive approximation register (SAR) analog-to-
digital converter (ADC) with a sampling rate of 1.7 GS/s at a power consumption of 1.38 mW …

A low-power SiGe BiCMOS 190-GHz receiver with 47-dB conversion gain and 11-dB noise figure for ultralarge-bandwidth applications

D Fritsche, G Tretter, P Stärke, C Carta… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
This paper presents a 190-GHz direct-conversion receiver capable of supporting higher
order modulation schemes and implemented in a 130-nm SiGe BiCMOS technology. The …

A 6-b 20-GS/s 2-way time-interleaved flash ADC with automatic comparator offset calibration in 28-nm FDSOI

Y Feng, H Deng, Q Fan, R Zhang… - … on Circuits and …, 2020 - ieeexplore.ieee.org
This paper presents a 6-bit 20 GS/s 2-way time-interleaved (TI) flash analog-to-digital
converter (ADC) in a 28-nm FDSOI CMOS technology. Leveraging threshold voltage control …

A 25-Gb/s 270-mW Time-to-Digital Converter-Based Oversampling Input-Delayed Data-Receiver in 45-nm SOI CMOS

SU Rehman, MM Khafaji, C Carta… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
This paper presents a time-to-digital converter-based oversampling input-delayed multi-
standard adaptable data-receiver architecture which digitizes transitions/threshold-crossings …

A 5-GS/s 6-bit 15.07-mW flash ADC with partially active second-stage comparison and 2× time-domain interpolation

Y Feng, H Deng, Q Fan, Y Tang… - … Transactions on Very …, 2022 - ieeexplore.ieee.org
This article presents a 5-GS/s 6-bit flash analog-to-digital converter (ADC) in a 28-nm fully
depleted silicon-on-insulator (FDSOI) CMOS process. The ADC jointly employs partially …

Design of Flash ADC using low offset comparator for analog signal processing application

A Yadav, N Rai, A Verma… - 2021 8th International …, 2021 - ieeexplore.ieee.org
The analog to digital converters (ADCs) are used in high bandwidth applications such as
communications, radar processing and data acquisition system. In this work, a 3-bit Flash …

A 2.4-GS/s power-efficient, high-resolution reconfigurable dynamic comparator for ADC architecture

G Raut, AP Shah, V Sharma, G Rajput… - Circuits, Systems, and …, 2020 - Springer
Reconfigurability is an important capability that provides flexibility in computing architecture
and low-power technique. It is challenging in digital-in-concept for designing smart analog …