Reviewing the evolution of the NAND flash technology
CM Compagnoni, A Goda, AS Spinelli… - Proceedings of the …, 2017 - ieeexplore.ieee.org
This paper reviews the recent historical trends of the NAND Flash technology, highlighting
the evolution of its main parameters and explaining what allowed it to become not only the …
the evolution of its main parameters and explaining what allowed it to become not only the …
Introduction to flash memory
R Bez, E Camerlenghi, A Modelli… - Proceedings of the …, 2003 - ieeexplore.ieee.org
This paper mainly focuses on the development of the NOR flash memory technology, with
the aim of describing both the basic functionality of the memory cell used so far and the main …
the aim of describing both the basic functionality of the memory cell used so far and the main …
Integrated circuit including memory array incorporating multiple types of NAND string structures
LG Fasoli, RE Scheuerlein - US Patent 7,177,191, 2007 - Google Patents
(57) ABSTRACT A monolithic integrated circuit includes a memory array having first and
second groups of NAND strings, each NAND string comprising at least two series-connected …
second groups of NAND strings, each NAND string comprising at least two series-connected …
On-chip error correcting techniques for new-generation flash memories
S Gregori, A Cabrini, O Khouri… - Proceedings of the …, 2003 - ieeexplore.ieee.org
In new-generation flash memories, issues such as disturbs and data retention become more
and more critical as a consequence of reduced cell size and decreased oxide thickness …
and more critical as a consequence of reduced cell size and decreased oxide thickness …
Nonvolatile semiconductor memory device
T Ono, Y Hirano, M Watanabe, SC Wong - US Patent 6,937,520, 2005 - Google Patents
The present invention relates to an electrically erasable and programmable nonvolatile
Semiconductor memory device comprising a memory cell array having a plurality of memory …
Semiconductor memory device comprising a memory cell array having a plurality of memory …
[图书][B] Floating gate devices: operation and compact modeling
P Pavan, L Larcher, A Marmiroli - 2007 - books.google.com
Floating Gate Devices: Operation and Compact Modeling focuses on standard operations
and compact modeling of memory devices based on Floating Gate architecture. Floating …
and compact modeling of memory devices based on Floating Gate architecture. Floating …
[PDF][PDF] On the use of strong BCH codes for improving multilevel NAND flash memory storage capacity
F Sun, K Rose, T Zhang - IEEE Workshop on Signal Processing Systems …, 2006 - Citeseer
This paper investigates the potential of using strong BCH codes to improve multilevel data-
storage NAND Flash memory capacity. Current multilevel Flash memories store 2 bits in …
storage NAND Flash memory capacity. Current multilevel Flash memories store 2 bits in …
An overview of flash architectural developments
G Campardo, M Scotti, S Scommegna… - Proceedings of the …, 2003 - ieeexplore.ieee.org
This paper presents a survey of the principal architectures and blocks building up a flash
memory, describing how these blocks are designed and how their design has changed over …
memory, describing how these blocks are designed and how their design has changed over …
Ssd architecture and pci express interface
K Eshghi, R Micheloni - Inside solid state drives (SSDs), 2013 - Springer
Flash-memory-based solid-state disks (SSDs) provide faster random access and data
transfer rates than electromechanical drives and today can often serve as rotating-disk …
transfer rates than electromechanical drives and today can often serve as rotating-disk …