BACKGROUND 0002 As integrated circuit (IC) design continues to evolve, one of the
important barriers to improved IC per formance is RC time delay. Such delay is induced, in …

2. Description of Related Art Because of continuing decreases in size of circuit com ponents
in semiconductor chips, there are a number of interconnect wiring challenges facing the …

(51) Int. Cl. substantially surrounded by air except for the discrete HOIL 23/248(2006.01)
regions of the Support dielectric and the optional intercon HOIL 23/52(2006.01) nect vias …

US6930034B2 - Robust ultra-low k interconnect structures using bridge-then-metallization
fabrication sequence - Google Patents US6930034B2 - Robust ultra-low k interconnect …

6,001.414 A 12/1999 Huang et al. 6.228, 770 B1 5/2001 Pradeep et al. 6,004,883. A
12/1999 Yu et al. 6,242,336 B1 6/2001 Ueda et al. 6,017,817 A 1/2000 Chung et al. 6.252 …

(57) ABSTRACT A method includes forming a line feature above a Substrate. Carbon-
containing spacers are formed on sidewalls of the line feature. A first dielectric layer is …

A semiconductor device includes a substrate, a gate dielec tric layer on the substrate, and a
gate electrode stack on the gate dielectric layer. The gate electrode stack includes a metal …

An electronic device having a substrate structure having an undercut region is provided and
further included is a method for forming an undercut region of a Substrate structure. The …

28 34 reducing capacitance in a dual damascene based interconnect structure is disclosed.
The air gap extends above, and may also additionally extend below, the damascene …

Such structure are disclosed. A composite dielectric layer comprising a porous matrix, as
well as a porogen in certain variations, is formed adjacent a Sacrificial dielectric layer …