Building timing predictable embedded systems
A large class of embedded systems is distinguished from general-purpose computing
systems by the need to satisfy strict requirements on timing, often under constraints on …
systems by the need to satisfy strict requirements on timing, often under constraints on …
MOHEFT: A multi-objective list-based method for workflow scheduling
Nowadays, scientists and companies are confronted with multiple competing goals such as
makespan in high-performance computing and economic cost in Clouds that have to be …
makespan in high-performance computing and economic cost in Clouds that have to be …
[LIVRE][B] The compiler design handbook: optimizations and machine code generation
YN Srikant, P Shankar - 2002 - taylorfrancis.com
The widespread use of object-oriented languages and Internet security concerns are just the
beginning. Add embedded systems, multiple memory banks, highly pipelined units …
beginning. Add embedded systems, multiple memory banks, highly pipelined units …
Nocalert: An on-line and real-time fault detection mechanism for network-on-chip architectures
The widespread proliferation of the Chip Multi-Processor (CMP) paradigm has cemented the
criticality of the on-chip interconnection fabric. The Network-on-Chip (NoC) is becoming …
criticality of the on-chip interconnection fabric. The Network-on-Chip (NoC) is becoming …
Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparison
I Puaut, C Pais - 2007 Design, Automation & Test in Europe …, 2007 - ieeexplore.ieee.org
We propose in this paper an algorithm for off-line selection of the contents of on-chip
memories. The algorithm supports two types of on-chip memories, namely locked caches …
memories. The algorithm supports two types of on-chip memories, namely locked caches …
A compiler framework for the reduction of worst-case execution times
H Falk, P Lokuciejewski - Real-Time Systems, 2010 - Springer
The current practice to design software for real-time systems is tedious. There is almost no
tool support that assists the designer in automatically deriving safe bounds of the worst-case …
tool support that assists the designer in automatically deriving safe bounds of the worst-case …
Optimal static WCET-aware scratchpad allocation of program code
H Falk, JC Kleinsorge - Proceedings of the 46th Annual Design …, 2009 - dl.acm.org
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a
memory access will result in a definite cache hit or miss. This unpredictability is highly …
memory access will result in a definite cache hit or miss. This unpredictability is highly …
WCET-directed dynamic scratchpad memory allocation of data
JF Deverge, I Puaut - … on Real-Time Systems (ECRTS'07), 2007 - ieeexplore.ieee.org
Many embedded systems feature processors coupled with a small and fast scratchpad
memory. To the difference with caches, allocation of data to scratchpad memory must be …
memory. To the difference with caches, allocation of data to scratchpad memory must be …
[PDF][PDF] Time-predictable computer architecture
M Schoeberl - EURASIP Journal on Embedded Systems, 2009 - Springer
Today's general-purpose processors are optimized for maximum throughput. Real-time
systems need a processor with both a reasonable and a known worst-case execution time …
systems need a processor with both a reasonable and a known worst-case execution time …
WCET-centric software-controlled instruction caches for hard real-time systems
I Puaut - 18th Euromicro Conference on Real-Time Systems …, 2006 - ieeexplore.ieee.org
Cache memories have been extensively used to bridge the gap between high speed
processors and relatively slower main memories. However, they are sources of predictability …
processors and relatively slower main memories. However, they are sources of predictability …