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Machine learning techniques in analog/RF integrated circuit design, synthesis, layout, and test
Rapid developments in semiconductor technology have substantially increased the
computational capability of computers. As a result of this and recent developments in theory …
computational capability of computers. As a result of this and recent developments in theory …
Analog integrated circuit routing techniques: An extensive review
Routing techniques for analog and radio-frequency (A/RF) integrated circuit (IC) design
automation have been proposed in the literature for over three decades. On those, an …
automation have been proposed in the literature for over three decades. On those, an …
Taskflow: A lightweight parallel and heterogeneous task graph computing system
Taskflow aims to streamline the building of parallel and heterogeneous applications using a
lightweight task graph-based approach. Taskflow introduces an expressive task graph …
lightweight task graph-based approach. Taskflow introduces an expressive task graph …
ALIGN: A system for automating analog layout
ALIGN: A System for Automating Analog Layout Page 1 8 2168-2356/20©2020 IEEE
Copublished by the IEEE CEDA, IEEE CASS, IEEE SSCS, and TTTC IEEE Design&Test …
Copublished by the IEEE CEDA, IEEE CASS, IEEE SSCS, and TTTC IEEE Design&Test …
MAGICAL: An open-source fully automated analog IC layout system from netlist to GDSII
MAGICAL: An Open-Source Fully Automated Analog IC Layout System from Netlist to GDSII
Page 1 2168-2356 (c) 2020 IEEE. Personal use is permitted, but republication/redistribution …
Page 1 2168-2356 (c) 2020 IEEE. Personal use is permitted, but republication/redistribution …
Towards decrypting the art of analog layout: Placement quality prediction via transfer learning
Despite tremendous efforts in analog layout automation, little adoption has been
demonstrated in practical design flows. Traditional analog layout synthesis tools use various …
demonstrated in practical design flows. Traditional analog layout synthesis tools use various …
Universal symmetry constraint extraction for analog and mixed-signal circuits with graph neural networks
Recent research trends in analog layout synthesis aim for a fully automated netlist-to-GDSII
design flow with minimum human efforts. Due to the sensitiveness of analog circuit layouts …
design flow with minimum human efforts. Due to the sensitiveness of analog circuit layouts …
Automatic op-amp generation from specification to layout
J Lu, L Lei, J Huang, F Yang, L Shang… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
The operational amplifier is a key building block in analog systems. However, the design
process of the operational amplifier is time consuming and heavily depends on engineers' …
process of the operational amplifier is time consuming and heavily depends on engineers' …
Fast surrogate-assisted constrained multiobjective optimization for analog circuit sizing via self-adaptive incremental learning
S Yin, R Wang, J Zhang, X Liu… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
In this article, we propose an efficient surrogate-assisted constrained multiobjective
evolutionary algorithm for analog circuit sizing via self-adaptive incremental learning. The …
evolutionary algorithm for analog circuit sizing via self-adaptive incremental learning. The …
Advancing placement
AB Kahng - Proceedings of the 2021 International Symposium on …, 2021 - dl.acm.org
Placement is central to IC physical design: it determines spatial embedding, and hence
parasitics and performance. From coarse-to fine-grain, placement is conjointly optimized …
parasitics and performance. From coarse-to fine-grain, placement is conjointly optimized …