Every day, billions of people depend on Internet services for communication, commerce, and
entertainment. Yet planetary-scale data center infrastructures consisting of millions of …

Transient or soft errors caused by various environmental effects are a growing concern in
micro and nanoelectronics. We present a general framework for modeling and mitigating the …

Branch prediction units (BPUs) are highly efficient modules that can significantly decrease
the negative impact of branches in pipelined processors. Traditional test solutions, mainly …

A growing portion of the silicon area of modern high-performance microprocessors is
dedicated to components that increase performance but do not determine functional …

To provide a new avenue for improving yield for nano-scale fabrication processes, we
introduce a new notion: performance degrading faults (pdef). A fault is said to be a pdef if it …

Speculative execution of instructions boosts performance in modern microprocessors.
Control and data flow dependencies are overcome through speculation mechanisms, such …

This paper presents a first-order analytical model for determining the performance
degradation caused by permanently faulty cells in architectural and non-architectural arrays …

Acceptable faults in a circuit under test (CUT) refer to those faults that have no or only minor
impacts on the performance of the CUT. A circuit with an acceptable fault may be marketable …

This paper presents a novel error-tolerance-based test methodology to grade defective
chips according to their degree of acceptability so as to improve the effective yield of chips …

Towards improving performance, modern microprocessors incorporate a variety of
architectural features, such as branch prediction and speculative execution, which are not …