This paper reviews the status of research in modeling and simulation of single-event effects
(SEE) in digital devices and integrated circuits, with a special emphasis on the current …

The rapid cadence of metal-oxide semiconductor field-effect transistor (MOSFET) scaling, as
seen in the new 2003 International Technology Roadmap for Semiconductors ITRS), is …

This paper describes the evolution of the SOI MOSFET from single-gate structures to
multigate (double-gate, trigate, Π-gate, Ω-gate and gate-all-around) structures. Increasing …

The paradigm and the usage of CMOS are changing, and so are the requirements at all
levels, from transistor to an entire CMOS system. The traditional drivers, such as speed and …

Soft errors are a multifaceted issue at the crossroads of applied physics and engineering
sciences. Soft errors are by nature multiscale and multiphysics problems that combine not …

As device scaling is entering the sub-25nm range, multiple gate device architectures are
needed to fulfill the ITRS requirements, since they offer a greatly improved electrostatic …

This paper focuses on total ionizing dose (TID) effects induced in multiple-gate field-effect
transistors. The impact of device architecture, geometry and scaling on the TID response of …

A new mobility degradation specific to short channel MOSFETs is studied and elucidated.
Pocket implants/dopants pile-up, interface states/oxide charges, remote Coulomb scattering …

(57) ABSTRACT A semiconductor device includes a semiconductor Substrate, a channel
region formed above the semiconductor Substrate, a first gate electrode formed above the …

We have performed a simulation study of symmetric ultrathin-body double-gate (SUTBDG)
devices with metal source/drain (S/D) structures designed for low-operating-power …