In this paper, we exploit an idea of coupling multiple oscillators to reduce phase noise (PN)
to beyond the limit of what has been practically achievable so far in a bulk CMOS …

This paper presents two class-C CMOS VCOs with a dynamic bias of the core transistors,
which maximizes the oscillation amplitude without compromising the robustness of the …

In this paper, we propose a new class of operation of an RF oscillator that minimizes its
phase noise. The main idea is to enforce a clipped voltage waveform around the LC tank by …

This paper presents a mm-wave subharmonic injection-locked (SHIL) fractional-N frequency
synthesizer for wireless multiband point-to-point backhaul communications. The SHIL …

We present an analog subsampling PLL based on a digital-to-time converter (DTC), which
operates with almost no performance gap (176/198 fs RMS jitter) between the integer and …

This paper introduces an ultra-low power 1.7-2.7-GHz fractional-N sub-sampling digital PLL
(SS-DPLL) for Internet-of-Things (IoT) applications targeting compliance with Bluetooth Low …

This article presents a wideband blocker tolerant receiver (RX) for fifth-generation (5G) user
equipment applications. Two programmable zeros around the channel bandwidth are …

An all-digital frequency synthesizer for cellular transmitter is presented. Low phase-noise is
achieved both in-band and out-of-band exploiting a 2-dimensional Vernier time-to-digital …

The design of very-wide-band CMOS voltage-controlled oscillators (VCOs) compliant with
the phase-noise specifications of cellular transmitters is non-trivial, especially considering …

A 2.8–3.2-GHz fractional-N digital PLL, implemented in 0.18-μm CMOS, is presented. The
PLL architecture has the form of a classic delta-sigma fractional-N PLL. A PFD generates up …