A 65 nm 2-billion transistor quad-core Itanium processor
B Stackhouse, S Bhimji, C Bostak… - IEEE Journal of Solid …, 2008 - ieeexplore.ieee.org
This paper describes an Itanium processor implemented in 65 nm process with 8 layers of
Cu interconnect. The 21.5 mm by 32.5 mm die has 2.05 B transistors. The processor has four …
Cu interconnect. The 21.5 mm by 32.5 mm die has 2.05 B transistors. The processor has four …
Safe limits on voltage reduction efficiency in GPUs: A direct measurement approach
Energy efficiency of GPU architectures has emerged as an important aspect of computer
system design. In this paper, we explore the energy benefits of reducing the GPU chip's …
system design. In this paper, we explore the energy benefits of reducing the GPU chip's …
Adaptive guardband scheduling to improve system-level efficiency of the POWER7+
The traditional guardbanding approach to ensure processor reliability is becoming obsolete
because it always over-provisions voltage and wastes a lot of energy. As a next-generation …
because it always over-provisions voltage and wastes a lot of energy. As a next-generation …
GPU voltage noise: Characterization and hierarchical smoothing of spatial and temporal voltage noise interference in GPU architectures
Energy efficiency is undoubtedly important for GPU architectures. Besides the traditionally
explored energy-efficiency optimization techniques, exploiting the supply voltage guard …
explored energy-efficiency optimization techniques, exploiting the supply voltage guard …
Pipeline muffling and a priori current ram**: architectural techniques to reduce high-frequency inductive noise
MD Powell, TN Vijaykumar - … of the 2003 international symposium on …, 2003 - dl.acm.org
While circuit and package designers have addressed microprocessor inductive noise issues
in the past, multi-gigahertz clock frequencies and billion-transistor-level integration are …
in the past, multi-gigahertz clock frequencies and billion-transistor-level integration are …
[BUCH][B] On and off-chip crosstalk avoidance in VLSI design
C Duan, BJ LaMeres, SP Khatri - 2010 - Springer
One of the greatest challenges in Deep Sub-Micron (DSM) design is inter-wire crosstalk,
which becomes significant with shrinking feature sizes of VLSI fabrication processes and …
which becomes significant with shrinking feature sizes of VLSI fabrication processes and …
Quantifying the relationship between the power delivery network and architectural policies in a 3D-stacked memory device
M Shevgoor, JS Kim, N Chatterjee… - Proceedings of the 46th …, 2013 - dl.acm.org
Many of the pins on a modern chip are used for power delivery. If fewer pins were used to
supply the same current, the wires and pins used for power delivery would have to carry …
supply the same current, the wires and pins used for power delivery would have to carry …
GPUVolt: Modeling and characterizing voltage noise in GPU architectures
Voltage noise is a major obstacle in improving processor energy efficiency because it
necessitates large operating voltage guardbands that increase overall power consumption …
necessitates large operating voltage guardbands that increase overall power consumption …
Exploiting resonant behavior to reduce inductive noise
MD Powell, TN Vijaykumar - ACM SIGARCH Computer Architecture …, 2004 - dl.acm.org
Inductive noise in high-performance microprocessors is a reliabilityissue caused by
variations in processor current (di/dt) which are converted to supply-voltage glitches by …
variations in processor current (di/dt) which are converted to supply-voltage glitches by …
Back to the future: Current-mode processor in the era of deeply scaled CMOS
This paper explores the use of MOS current-mode logic (MCML) as a fast and low noise
alternative to static CMOS circuits in microprocessors, thereby improving the performance …
alternative to static CMOS circuits in microprocessors, thereby improving the performance …