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High-efficient, ultra-low-power and high-speed 4: 2 compressor with a new full adder cell for bioelectronics applications
Size reduction in complementary metal–oxide–semiconductor integrated circuits (ICs) is a
challenge. Carbon nanotube field effect transistor (CNTFET) technology with advantages …
challenge. Carbon nanotube field effect transistor (CNTFET) technology with advantages …
Tolerant and low power subtractor with 4: 2 compressor and a new TG‐PTL‐float full adder cell
A new 1‐bit full adder (FA) cell illustrating low‐power, high‐speed, and a small area is
presented by a combination of transmission gate (TG), pass transistor logic (PTL), and float …
presented by a combination of transmission gate (TG), pass transistor logic (PTL), and float …
On the resiliency of NCFET circuits against voltage over-scaling
Approximate computing is established as a design alternative to improve the energy
requirements of a vast number of applications, leveraging their intrinsic error tolerance …
requirements of a vast number of applications, leveraging their intrinsic error tolerance …
Energy-efficient Hadamard-based SATD hardware architectures through calculation reuse
The Hadamard-based Sum of Absolute Transformed Differences (SATD) is a distortion
metric that correlates better with other video encoding steps than the commonly used Sum of …
metric that correlates better with other video encoding steps than the commonly used Sum of …
SAD or SATD? how the distortion metric impacts a Fractional Motion Estimation VLSI architecture
Video coding systems have to deal with a number of tradeoffs. The decision of adopting a
specific distortion metric in the Fractional Motion Estimation (FME) step, for instance …
specific distortion metric in the Fractional Motion Estimation (FME) step, for instance …
An efficient N-bit 8-2 adder compressor with a constant internal carry propagation delay
Adder compressors (AC) have been extensively used in digital circuits like multipliers and
transforms where several multi-bit operands have to be summed in parallel. Most available …
transforms where several multi-bit operands have to be summed in parallel. Most available …
Approximate SATD hardware accelerator using the 8× 8 Hadamard transform
MF Stigger, VHS Lima, LB Soares… - 2020 IEEE 11th Latin …, 2020 - ieeexplore.ieee.org
Sum of Absolute Transformed Differences (SATD) is a distortion metric based on the
Hadamard Transform. It is used in current video encoders inside the refinement stage of …
Hadamard Transform. It is used in current video encoders inside the refinement stage of …
A fast monolithic 8-2 adder compressor circuit
Adder compressor architectures have been widely used in multipliers and have recently
achieved improvements over conventional approaches in the computation of multiple …
achieved improvements over conventional approaches in the computation of multiple …
Configurable approximate hardware accelerator to compute SATD and SAD metrics for low power all-intra high efficiency video coding
VHS Lima, MF Stigger, LB Soares… - 2021 34th SBC …, 2021 - ieeexplore.ieee.org
Connecting billions of network cameras to the cloud is a challenge that heavily taxes the
network bandwidth for video transmissions. High Efficiency Video Coding (HEVC) standard …
network bandwidth for video transmissions. High Efficiency Video Coding (HEVC) standard …
High-level synthesis implementation of transform-exempted satd architectures for low-power video coding
T Partanen, A Lemmetti, P Sjövall… - 2021 IEEE International …, 2021 - ieeexplore.ieee.org
This paper presents the first known high-level synthesis (HLS) implementation for the Sum of
Absolute Transformed Differences (SATD) calculation. The proposed hardware architecture …
Absolute Transformed Differences (SATD) calculation. The proposed hardware architecture …