Various embodiments of a cache coherence protocol including write-only permission for
coherence units dis closed. According to one embodiment, a system may include a number …

9, 639, 469 B2 5/2017 Moll et al. 9, 652, 404 B2 5/2017 Pierson et al. 9, 727, 466 B2 8/2017
Tune et al. 9, 767, 026 B2 9/2017 Niell et al. 9, 817, 760 B2 11/2017 Robinson et al. 9, 830 …

BACKGROUND 0002 Computer system design involves several tradeoffs to maximize
performance while minimizing cost. For example, for many years effective processor speeds …

An interconnect and method of managing a Snoop filter within Such an interconnect are
provided. The interconnect is used to connect a plurality of devices, including a plurality of …

(57) ABSTRACT A data processing system includes a snoop filter organized as a number of
lines, each storing an address tag associated with the address of data stored in one or more …

BACKGROUND In a multi-processor System having multiple processors and multiple
caches, each cache may store a copy of a piece of data stored in memory. Problems arise …

An interconnect has coherency control circuitry for perform ing coherency control operations
and a Snoop filter for identifying which devices coupled to the interconnect have cached …

0002 Various arrangements for multiprocessor systems have been proposed. For example,
in a front-side bus system, multiple processors communicate data through a bidirectional …

The present disclosure includes a method of charging a battery. In one embodiment, the
method comprises receiv ing, in a battery charging circuit on an electronic device, an input …

System, method, and processor for enabling early dealloca tion of tracker entries which track
memory accesses are described herein. One embodiment of a method includes: maintaining …