Dielectric breakdown of oxide films in electronic devices
Dielectric breakdown is a sudden and catastrophic increase in the conductivity of an
insulator caused by electrical stress. It is one of the major reliability issues in electronic …
insulator caused by electrical stress. It is one of the major reliability issues in electronic …
Border traps in Ge/III–V channel devices: Analysis and reliability aspects
The aim of this review paper is to describe the impact of so-called border traps (BTs) in high-
k gate oxides on the operation and reliability of high-mobility channel transistors. First, a …
k gate oxides on the operation and reliability of high-mobility channel transistors. First, a …
[HTML][HTML] A simple figure of merit to identify the first layer to degrade and fail in dual layer SiOx/HfO2 gate dielectric stacks
Understanding the degradation dynamics and the breakdown sequence of a bilayer high-k
(HK) gate dielectric stack is crucial for the improvement of device reliability. We present a …
(HK) gate dielectric stack is crucial for the improvement of device reliability. We present a …
Breakdown in the metal/high-k gate stack: Identifying the “weak link” in the multilayer dielectric
G Bersuker, D Heh, C Young, H Park… - 2008 IEEE …, 2008 - ieeexplore.ieee.org
We apply a systematic approach to identify a high-k/metal gate stack degradation
mechanism. Our results demonstrate that the SiO 2 interfacial layer controls the overall …
mechanism. Our results demonstrate that the SiO 2 interfacial layer controls the overall …
Exploring the capability of multifrequency charge pum** in resolving location and energy levels of traps within dielectric
Multifrequency charge-pum** (MFCP) experiments have been used by many groups to
profile the locations and the energy levels of bulk traps within high-kappa gate dielectric …
profile the locations and the energy levels of bulk traps within high-kappa gate dielectric …
Applications of DCIV method to NBTI characterization
The DCIV method was applied to investigate negative bias temperature instability (NBTI) in
SiO2 gate oxides. The DCIV technique, which measures the interface defect density …
SiO2 gate oxides. The DCIV technique, which measures the interface defect density …
[BOOK][B] Electrical characterisation of ferroelectric field effect transistors based on ferroelectric HfO2 thin films
E Yurchuk - 2015 - books.google.com
Ferroelectric field effect transistor (FeFET) memories based on a new type of ferroelectric
material (silicon doped hafnium oxide) were studied within the scope of the present work …
material (silicon doped hafnium oxide) were studied within the scope of the present work …
Comprehensive study on the deep depletion capacitance-voltage behavior for metal-oxide-semiconductor capacitor with ultrathin oxides
The deep depletion behaviors at the structure of Si/SiO 2 with various equivalent oxide
thicknesses (EOTs) are comprehensively studied by magnified capacitance versus gate …
thicknesses (EOTs) are comprehensively studied by magnified capacitance versus gate …
Two-Pulse – : A New Method for Characterizing Electron Traps in the Bulk of Dielectric Stacks
SiO_2/high-κ dielectric stack is a candidate for replacing the conventional SiO_2-based
dielectric stacks for future Flash memory cells. Electron traps in the high-κ layer can limit the …
dielectric stacks for future Flash memory cells. Electron traps in the high-κ layer can limit the …
Temperature dependence of the emission and capture times of SiON individual traps after positive bias temperature stress
M Toledano-Luque, B Kaczer, P Roussel… - Journal of Vacuum …, 2011 - pubs.aip.org
The authors study the statistical properties of individual defects in n-type metal-oxide-
semiconductor field-effect transistors (nMOSFETs) using time dependent defect …
semiconductor field-effect transistors (nMOSFETs) using time dependent defect …