Reducing writebacks through in-cache displacement
Non-Volatile Memory (NVM) technology is a promising solution to fulfill the ever-growing
need for higher capacity in the main memory of modern systems. Despite having many great …
need for higher capacity in the main memory of modern systems. Despite having many great …
MORSE: Memory Overwrite Time Guided Soft Writes to Improve ReRAM Energy and Endurance
ReRAM is an attractive main memory technology due to its high density and low idle power.
However, ReRAM exhibits costly writes, especially in terms of energy and endurance. Prior …
However, ReRAM exhibits costly writes, especially in terms of energy and endurance. Prior …
HAP: Hybrid-memory-aware partition in shared last-level cache
Data-center servers benefit from large-capacity memory systems to run multiple processes
simultaneously. Hybrid DRAM-NVM memory is attractive for increasing memory capacity by …
simultaneously. Hybrid DRAM-NVM memory is attractive for increasing memory capacity by …
DyPhase: A dynamic phase change memory architecture with symmetric write latency and restorable endurance
A major challenge for the widespread adoption of phase change memory (PCM) as main
memory is its asymmetric write latency. Generally, for a PCM, the latency of a SET operation …
memory is its asymmetric write latency. Generally, for a PCM, the latency of a SET operation …
WALL: A writeback-aware LLC management for PCM-based main memory systems
In this paper, we propose WALL, a novel writeback-aware LLC management scheme to
reduce the number of LLC writebacks and consequently improve performance, energy …
reduce the number of LLC writebacks and consequently improve performance, energy …
Writeback-aware LLC management for PCM-based main memory systems
With the increase in the number of data-intensive applications on today's workloads, DRAM-
based main memories are struggling to satisfy the growing data demand capacity. Phase …
based main memories are struggling to satisfy the growing data demand capacity. Phase …
HSCS: A hybrid shared cache scheduling scheme for multiprogrammed workloads
The traditional dynamic random-access memory (DRAM) storage medium can be integrated
on chips via modern emerging 3D-stacking technology to architect a DRAM shared cache in …
on chips via modern emerging 3D-stacking technology to architect a DRAM shared cache in …
Crash recoverable ARMv8-oriented B+-tree for byte-addressable persistent memory
The byte-addressable non-volatile memory (NVM) promises persistent memory. Concretely,
ARM processors have incorporated architectural supports to utilize NVM. In this paper, we …
ARM processors have incorporated architectural supports to utilize NVM. In this paper, we …
Aware Cache Replacement Policy
KD Christidis - US Patent App. 14/965,132, 2017 - Google Patents
An aware cache replacement policy increases the length of in-page bursts of cache eviction
memory requests and promotes bank-rotation to reduce the likelihood of memory bank …
memory requests and promotes bank-rotation to reduce the likelihood of memory bank …
Branch-aware data variable allocation for energy optimization of hybrid SRAM+ NVM SPM☆
J Zhan, Y Li, W Jiang, J Yu, J Yu - Journal of Systems Architecture, 2020 - Elsevier
In this paper, we are interested in the energy optimization of hybrid Scratchpad Memory
(SPM) which consists of SRAM and Non-Volatile Memory (NVM). We approach the energy …
(SPM) which consists of SRAM and Non-Volatile Memory (NVM). We approach the energy …