Reducing writebacks through in-cache displacement

M Bakhshalipour, A Faraji, SAV Ghahani… - ACM Transactions on …, 2019 - dl.acm.org
Non-Volatile Memory (NVM) technology is a promising solution to fulfill the ever-growing
need for higher capacity in the main memory of modern systems. Despite having many great …

MORSE: Memory Overwrite Time Guided Soft Writes to Improve ReRAM Energy and Endurance

D Singh, D Yeung - Proceedings of the 2024 International Conference …, 2024 - dl.acm.org
ReRAM is an attractive main memory technology due to its high density and low idle power.
However, ReRAM exhibits costly writes, especially in terms of energy and endurance. Prior …

HAP: Hybrid-memory-aware partition in shared last-level cache

W Wei, D Jiang, J **ong, M Chen - ACM Transactions on Architecture …, 2017 - dl.acm.org
Data-center servers benefit from large-capacity memory systems to run multiple processes
simultaneously. Hybrid DRAM-NVM memory is attractive for increasing memory capacity by …

DyPhase: A dynamic phase change memory architecture with symmetric write latency and restorable endurance

IG Thakkar, S Pasricha - IEEE Transactions on Computer-Aided …, 2017 - ieeexplore.ieee.org
A major challenge for the widespread adoption of phase change memory (PCM) as main
memory is its asymmetric write latency. Generally, for a PCM, the latency of a SET operation …

WALL: A writeback-aware LLC management for PCM-based main memory systems

B Pourshirazi, MV Beigi, Z Zhu… - … Design, Automation & …, 2018 - ieeexplore.ieee.org
In this paper, we propose WALL, a novel writeback-aware LLC management scheme to
reduce the number of LLC writebacks and consequently improve performance, energy …

Writeback-aware LLC management for PCM-based main memory systems

B Pourshirazi, MV Beigi, Z Zhu, G Memik - ACM Transactions on Design …, 2019 - dl.acm.org
With the increase in the number of data-intensive applications on today's workloads, DRAM-
based main memories are struggling to satisfy the growing data demand capacity. Phase …

HSCS: A hybrid shared cache scheduling scheme for multiprogrammed workloads

J Zhang, C Wu, D Yang, Y Chen, X Meng, L Xu… - Frontiers of Computer …, 2018 - Springer
The traditional dynamic random-access memory (DRAM) storage medium can be integrated
on chips via modern emerging 3D-stacking technology to architect a DRAM shared cache in …

Crash recoverable ARMv8-oriented B+-tree for byte-addressable persistent memory

C Wang, S Chattopadhyay… - Proceedings of the 20th …, 2019 - dl.acm.org
The byte-addressable non-volatile memory (NVM) promises persistent memory. Concretely,
ARM processors have incorporated architectural supports to utilize NVM. In this paper, we …

Aware Cache Replacement Policy

KD Christidis - US Patent App. 14/965,132, 2017 - Google Patents
An aware cache replacement policy increases the length of in-page bursts of cache eviction
memory requests and promotes bank-rotation to reduce the likelihood of memory bank …

Branch-aware data variable allocation for energy optimization of hybrid SRAM+ NVM SPM☆

J Zhan, Y Li, W Jiang, J Yu, J Yu - Journal of Systems Architecture, 2020 - Elsevier
In this paper, we are interested in the energy optimization of hybrid Scratchpad Memory
(SPM) which consists of SRAM and Non-Volatile Memory (NVM). We approach the energy …