A dynamic jitter model to evaluate uncertainty trends with technology scaling
Clock jitter can no longer be considered negligible when compared to clock skew. Its
unpredictability and high-frequency content makes it an increasingly limiting factor to …
unpredictability and high-frequency content makes it an increasingly limiting factor to …
A jitter insertion and accumulation model for clock repeaters
This paper presents a model to estimate jitter insertion and accumulation in clock repeaters.
We propose expressions to estimate, with low computational effort, both static and dynamic …
We propose expressions to estimate, with low computational effort, both static and dynamic …
Uncertainty in DLL deskewing schemes
This paper proposes an analytical model to evaluate deskewing uncertainty, considering
floorplanning and scalability issues. It can be a helpful tool in evaluating the potential gains …
floorplanning and scalability issues. It can be a helpful tool in evaluating the potential gains …
Synchronisation in high-performance integrated circuits
MJC de Figueiredo - 2012 - search.proquest.com
A distribui ção de um sinal relógio, com elevada precisão espacial (baixo skew) e temporal
(baixo jitter), em sistemas sí ncronos de alta velocidade tem-se revelado uma tarefa cada …
(baixo jitter), em sistemas sí ncronos de alta velocidade tem-se revelado uma tarefa cada …